3 Pin Description
The functions of the device pins are described in Table 3-1.
| Pin Name | Pin Function |
|---|---|
| CE# | Chip Enable |
| SIO[3:0] | Transfers commands, addresses or data serially into and out of the device. Inputs are latched on the rising edge of the serial clock, and data are shifted out on the falling edge. The Enable Quad I/O (EQIO) command configures these pins for Quad I/O mode. |
| SI | Transfers commands, addresses or data serially into the device. Inputs are latched on the rising edge of the serial clock. SI is the default state after a Power-On Reset (POR) or hardware reset. |
| SO | Transfers data serially out of the device. Data are shifted out on the falling edge of the serial clock. SO is the default state after power-on. |
| VSS | Ground |
| WP# | Write Protect. Used in conjunction with the WPEN and IOC bits in the Configuration register to prohibit write operations to the volatile and nonvolatile protection bytes. This pin operates only in single-bit SPI mode. |
| SCK | Serial clock input |
| HOLD# | Temporarily suspends serial communication with the SPI Flash memory while the device is selected. This pin operates only in single-bit SPI mode and must be tied high when not in use. |
| RESET# | Reset device operation and internal logic. Includes an internal pull-up resistor. |
| VCC | +2.7V to +3.6V power supply |