3 Pin Allocation Tables

Table 3-1. 28-Pin Allocation Table
I/O(2) 28-

Pin

SPDIP,

SOIC, SSOP

28-

Pin

VQFN

A/D Reference Comparator ZCD Timers 16-Bit PWM/

CCP

CWG CLC SPI I2C UART IOC Interrupt Basic

RA0

2

27

ANA0

C1IN0-

C2IN0-

CLCIN0(1)

CLCIN4(1)

IOCA0

RA1

3

28

ANA1

C1IN1-

C2IN1-

CLCIN1(1)

CLCIN5(1)

IOCA1

RA2

4

1

ANA2

DAC1OUT1

VREF- (DAC1)

VREF- (ADC)

C1IN0+

C2IN0+

IOCA2

RA3

5

2

ANA3

VREF+ (DAC1)

VREF+ (ADC)

C1IN1+

IOCA3

RA4

6

3

ANA4 T0CKI(1)

IOCA4

RA5

7

4

ANA5

SS1(1)

IOCA5

RA6

10

7

ANA6

IOCA6

CLKOUT

OSC2

RA7

9

6

ANA7

IOCA7

OSC1

CLKIN

RB0

21

18

ANB0

C2IN1+

ZCDIN

CWG1(1)

SS2(1)

IOCB0

INT0(1)

RB1 22 19 ANB1

C1IN3-

C2IN3-

SCK2(1) SCL2(3,4) IOCB1

INT1(1)

RB2 23 20 ANB2 SDI1(1) SDA2(3,4) IOCB2

INT2(1)

RB3 24 21 ANB3

C1IN2-

C2IN2-

IOCB3
RB4 25 22

ANB4

ADACT(1)

IOCB4
RB5 26 23 ANB5

T1G(1)

TUIN1(1)

IOCB5
RB6 27 24 ANB6

CLCIN2(1)

CLCIN6(1)

CTS2(1) IOCB6 ICSPCLK
RB7 28 25 ANB7 DAC1OUT2 T6IN(1) PWM3ERS(1)

CLCIN3(1)

CLCIN7(1)

RX2(1) IOCB7 ICSPDAT
RC0 11 8 ANC0

T1CKI(1)

T3CKI(1)

T3G(1)

TUIN0(1)

IOCC0 SOSCO
RC1 12 9 ANC1 CCP2(1) IOCC1 SOSCI
RC2 13 10 ANC2 ZCD2IN

PWMIN0(1)

CCP1(1)

IOCC2
RC3(6) 14 11 T2IN(1) PWM1ERS(1) SCK1(1) SCL1(3,4) IOCC3
RC4(6) 15 12 SDI1(1) SDA1(3,4) IOCC4
RC5(6) 16 13

T4IN(1) PWM2ERS(1) RX1(1) IOCC5
RC6(6) 17 14 PWMIN1(1) CTS1(1) IOCC6
RE3 1 26 IOCE3 VPP/MCLR
VDD(5) 20 17 VDD(5)
VDDIO2(5) 18 15 VDDIO2
VSS 8, 19 5, 16 VSS
OUT(2)

ADGRDA

ADGRDB

C1OUT

C2OUT

TMR0

PWM11

PWM12

PWM21

PWM22

PWM31

PWM32

CCP1

CCP2

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

CLC5OUT

CLC6OUT

CLC7OUT

CLC8OUT

SS1

SCK1

SDO1

SDA1

SCL1

SDA2

SCL2

DTR1

RTS1

TX1

DTR2

RTS2

TX2

Note:
  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal.
  2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
  3. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers.
  4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. A 0.1 μF bypass capacitor to VSS is required on the VDD and VDDIOx pins.
  6. MVIO pins, powered by VDDIO2.