1.1.1 ADC Conversion

When using the ADCRC as the clock source for ADCC, there is a delay of one instruction cycle between setting the ADGO bit and being able to read it as set. This delay may result in a false conversion complete scenario (i.e., ADGO being cleared), particularly if the user code has a bit clear test BTFSC instruction on the ADGO bit immediately after setting it. See code example below.

BSF ADCON0, ADGO                    ;    Start conversion
BTSFC ADCON0, ADGO                  ;    Is conversion done?
GOTO $-1                            ;    No, test again

Work around

Add a NOP instruction after setting the ADGO bit and before testing the bit for completion of conversion. See code example below.

BSF ADCON0, ADGO                    ;    Start conversion
NOP
BTSFC ADCON0, ADGO                  ;    Is conversion done?
GOTO $-1                            ;    No, test again

Affected Silicon Revisions