3.5 Crystal Routing

This section describes the recommended layout guidelines with respect to crystal routing:

1. Keep the traces from the device pads to the crystal as short as possible.
2. Place the guard ground vias all along the trace routed to crystal. See Figure 3-15 for the entire area around the trace to pin 14 (XO_N) and pin 15 (XO_P).
3. Surround the area around the crystal with ground polygon pour, and place sufficient ground vias in this polygon pour.
4. Do not route any signal traces below the crystal area in all the other layers. Also, do not route any signal traces adjacent to the crystal trace. Specific care must be taken to isolate any known noisy signal traces, such as GPIOs intended to be fast toggling, from crystal traces with proper polygon ground pour and sufficient GND vias.