3.3 Power Supply

This section describes the recommended layout guidelines with respect to the power supply.

  1. Place the decoupling capacitors as close to the device pin as possible. The following figure illustrates the best possible placement of all the decoupling capacitors for the PIC32CX1012BZ24032 design.
    Figure 3-1. Top Layer Overlayed with Top Assembly
  2. Ensure the loop formed by the trace from pin 32 (PMU_BUCK_BK_LX), PMU switching inductor (L1), decoupling capacitor (C7), pin 2 (PMU_MLDO) and decoupling capacitor (C6) is as short as possible. The following figure illustrates the best placement for these components. It is recommended to replicate this placement in the design. Ensure the trace from C7 to pin 2 (PMU_MLDO) is routed through a via to inner layer 3.
    Note: The trace is intentionally routed such that the trace after via might pass through C6 before routing to pin 2. This allows for better filtering.
    Figure 3-2. PMU Output Loop
  3. All power supply traces must have thick copper traces or planes to keep the DC Resistance as low as possible.
  4. All decoupling capacitors must have a dedicated ground via placed next to the GND pad of the capacitor.
    Figure 3-3. Power Traces and GND Via
  5. For the connection from the primary supply trace VDD and VDD_M, use redundant vias for connecting between layers as highlighted (in yellow) in the following figure. Also, it is recommended that large vias be used for the power supply trace to lower the inductance. The recommended via size might be 8/16 mil (hole size/diameter).
    Figure 3-4. Power Supply Routing Vias
  6. Inner layer 1 must be fully dedicated to GND and must not be used for routing signal/power traces. The bottom side of the PCB antenna must be free from copper. Keep enough clearance on all the layers as per the antenna recommendation. Also, the U.FL connector area must not have any conductive traces; therefore, keep the polygon cutout on this area, otherwise, it impacts the impedance matching for the U.FL antenna.
    Figure 3-5. Inner Layer 1 (GND)
  7. Use inner layer 2 for power and signal routing. Fill the unused areas with the GND copper pour.
    Figure 3-6. Inner Layer 2
    Figure 3-7. Bottom Layer Overlaid with Top Assembly
  8. Figure 3-7 shows the routing of the VDD_M and VDD_1P35V traces in the bottom layer with the top assembly overlaid. Ensure the routing topology for VDD_1P35V as in the reference design with a star topology ensuring the lowest IR drop for the power rail routed to the power supply pins. Routing the VDD_1P35V trace to the following pins with isolated traces is recommended as follows:
    1. Pin 11 (BUCK_CLDO), pin 13 (BUCK_BB) and pin 17 (BUCK_LPA)
    2. Pin 16 (BUCK_PLL)
  9. The VDD_1P35V trace of pin 16 (BUCK_PLL) is intentionally separated from trace to pin 11 (BUCK_CLDO), pin 13 (BUCK_BB) and pin 17 (BUCK_LPA). This is done to avoid coupling of any noise onto BUCK_PLL. Also, wherever possible, these two adjacent VDD_1P35V traces in the bottom layer were isolated with GND polygon pour and vias.
  10. The GND paddle of the device must be connected to the GND of the host board through a grid of 4x4 vias with a minimum via size of 6/14 mil (hole size/diameter). The same is shown in the following figure. The vias are to be evenly spread out by about 1.2 mm from each other. This allows for a better GND connection and helps with improved thermal performance.
    Figure 3-8. Recommended GND via Placement for GND Paddle
  11. Place sufficient GND vias throughout the board in feasible areas to ensure the least possible inductance to the ground path.
  12. Place GND vias at the edge of the design to improve the ESD/EMC performance.