27.1.1 Application Core (CM4-C0) Matrix 0 and 1 Hosts and Clients
| Host No. | Host Name | Description |
|---|---|---|
| 0 | CM4-C0 ICode Bus | – |
| 1 | CM4-C0 DCode Bus | – |
| 2 | CM4-C0 S-Bus | – |
| 3 | CMCC0 (ICache/ITCM) | – |
| 4 | CMCC1 (DCache/DTCM) | – |
| 5 | MATRIX2 | CM4-C1 S-Bus, PDC1 |
| 6 | MATRIX1 | PDC0, PDC2 and ICM |
| Client No. | Client Name | Description |
|---|---|---|
| 0 | SRAM0, Port 0 | – |
| 1 | SRAM0, Port 1 | – |
| 2 | SRAM0, Port 2 | – |
| 3 | ROM | – |
| 4 | MATRIX1 | Provides access to:
|
| 5 | CPKCC | – |
| 6 | APB Bridge 3 | – |
| 7 | MATRIX2 | Provides access to:
|
| 8 | CMCC0 (ICache/ITCM) | – |
| 9 | CMCC1 (DCache/DTCM) | – |
| 10 | Flash | – |
| 11 | MATRIX1 | Provides access to:
|
Note: For consistency, each SRAM port shall have the same Privilege Protection access
management configuration.
| MATRIX0 Clients | MATRIX0 Hosts | |||||||
|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | ||
| CM4-C0 ICode Bus | CM4-C0 DCode Bus | CM4-C0 S-Bus | CMCC0 (ICache/ITCM) | CMCC1 (DCache/DTCM | MATRIX2 | MATRIX1 | ||
| 0 | SRAM0, Port 0 | – | – | X | – | – | – | – |
| 1 | SRAM0, Port 1 | – | – | – | – | – | – | X |
| 2 | SRAM0, Port 2 | – | – | – | – | – | X | – |
| 3 | ROM | X | X | – | – | – | – | – |
| 4 | MATRIX1 | X | X | X | – | – | X | – |
| 5 | CPKCC | X | X | – | – | – | – | – |
| 6 | APB Bridge 3 | – | – | X | – | – | X(5) | – |
| 7 | MATRIX2 | – | – | X | – | – | – | X(2) |
| 8 | CMCC0 (ICache/ITCM) | X | X(3) | – | – | – | – | – |
| 9 | CMCC1 (DCache/DTCM) | – | X | – | – | – | – | – |
| 10 | Flash(4) | X | X | X(6) | X | X | – | X |
| 11 | MATRIX1 | – | – | – | X | X | – | – |
Note:
- For consistency, each SRAM port shall have the same Privilege Protection access management configuration.
- Through this port, PDC0, PDC2, and ICM can only access port 3 of SRAM1 and 2.
- Connection needed to enable write of ITCM for CM4-C0.
- Client Flash must be configured in NO_DEFAULT_MASTER.
- Only CM4P1-S has access to APB Bridge 3 through HSMS2HSASB.
- Used to access the Flash Controller Page Buffer (Write Operation) in a strongly ordered manner.
| Host No. | Host Name | Description |
|---|---|---|
| 0 | MATRIX0 |
|
| 1 | MATRIX0 | CMCC0 (I), CMCC1 (D) to QSPI and AESB |
| 2 | AESB | QSPI Cached or Non cached through AESB |
| 3 | ICM |
Flash Non cached QSPI Non cached SRAM0 port1 SRAM1 port3 SRAM2 port3 |
| 4 | PDC0 |
QSPI Non cached AESB Non cached - through AESB SRAM0 port1 SRAM1 port3 SRAM2 port3 |
| 5 | PDC2 |
Flash Non cached QSPI Non cached SRAM0 port1 SRAM1 port3 SRAM2 port3 |
| Client No. | Client Name | Description |
|---|---|---|
| 0 | QSPI | – |
| 1 | AESB | – |
| 2 | MATRIX0 | Provides access to:
|
| 3 | APB Bridge 0 | – |
| 4 | APB Bridge 2 | – |
| MATRIX1 Clients | MATRIX1 Hosts | ||||||
|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | ||
| MATRIX0 | MATRIX0 | AESB | ICM | PDC0 | PDC2 | ||
| 0 | QSPI | X | X | X | X | X | X |
| 1 | AESB | X | X | – | – | X | – |
| 2 | MATRIX0 | – | – | – | X | X | X |
| 3 | APB Bridge 0 | X | – | – | – | X | – |
| 4 | APB Bridge 2 | X | – | – | – | – | X |