3.3 Watchdog Timer Control Register
Name: | WDTCR |
Offset: | - |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WDTOE | WDE | WDP[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – WDTOE Watchdog Turn-off Enable
Set this bit when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.
Bit 3 – WDE Watchdog Enable
- In the same operation, write a logic one to WDTOE and WDE. Write a logic one to WDE even though it is set to one before the disable operation starts.
- Within the following four clock cycles, write a logic 0 to WDE, which disables the Watchdog.
Bits 2:0 – WDP[2:0] Watchdog Timer Prescaler
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The table below shows the different prescaling values and their corresponding Timeout Periods.
WDP2 | WDP1 | WDP0 | Number of WDT Oscillator Cycles | Typical Time-Out at VCC = 3.0V | Typical Time-Out at VCC = 5.0V |
---|---|---|---|---|---|
0 | 0 | 0 | 16K (16,384) | 14 ms | 13 ms |
0 | 0 | 1 | 32K (32,768) | 28 ms | 26 ms |
0 | 1 | 0 | 64K (65,536) | 56 ms | 52 ms |
0 | 1 | 1 | 128K (131,072) | 0.11s | 0.10s |
1 | 0 | 0 | 256K (262,144) | 0.22s | 0.21s |
1 | 0 | 1 | 512K (524,288) | 0.45s | 0.42s |
1 | 1 | 0 | 1,024K (1,048,576) | 0.89s | 0.84s |
1 | 1 | 1 | 2,048K (2,097,152) | 1.8s | 1.7s |
The following code example shows one assembly and one C function for turning off the WDT. It assumes that interrupts are controlled (e.g, by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example |
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WDT_off: ; reset WDT wdr ; Write logical one to WDTOE and WDE in r16, WDTCR ori r16, (1<<WDTOE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret |
C Code Example |
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void WDT_off(void) { /* reset WDT */ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } |