When the DMA module is enabled and all setup is complete, the DMA transfer can be initiated by setting the DGO bit in the DMAxCON0 register.
Based on the system arbiter priority settings, when a CPU cycle is granted, the DMA module will read a byte of data from the source address and transfer it to the DMAxBUF register. The XIP bit in the DMAxCON0 register is also set, indicating that a transfer is in progress. When the DMA module gets another CPU cycle grant, the data is moved to the destination address and the XIP bit is cleared.