To achieve a reasonable level of long term jitter, deliver an analog grade power supply to the PLL. An R-C or R-L-C filter is used with the C being composed of multiple devices to achieve a wide spectrum of noise absorption. Even the circuit is simple, there are specific board layout requirements. Board layout around the high-frequency capacitor and the path to the pads are critical. It is vital that the quiet ground and power are treated like analog signals. The entire VDDPLL and PLLVSSA wiring path must not be coupled with any signal aggressors, such as any high-swing and high slew rate signals such as TTL, CMOS, or SSTL signals used in DDR buses, and so on.

The circuit for the power supply filter is shown in the following figure.

Figure 1. Filter Circuit for PLL

For more information about R1, C1, and C2, see Design Considerations.