This section provides guidelines for the hardware board layout that incorporates SmartFusion2 SoC FPGA or IGLOO2 FPGA devices. Good board layout practices are required to achieve the expected performance from the printed circuit boards (PCB) and SmartFusion2/IGLOO2 devices. These are essential to achieve high quality and reliable results such as low-noise levels, signal integrity, impedance, and power requirements. The guidelines mentioned in this document act as a supplement to the standard board-level layout practices.
Understanding of the SmartFusion2/IGLOO2 chip, experience in digital and analog board layout, and knowledge of transmission line theory and signal integrity is needed. For more information about the recommended guidelines for designing SmartFusion2/IGLOO2-based boards, see Design Considerations.
The target impedance calculated in this document is with respect to the development board. The simulations show the impedance that meets the target impedance of the development board. The target impedance depends on the logic implemented on SmartFusion2/IGLOO2. Therefore, calculate the target impedance of the board.