Audio Frequency Shift Keying Demodulator

The first application to be considered is an audio frequency shift keying (AFSK) demodulator for the Specific Area Message Encoding (SAME) protocol, running on the AVR® ATmega328P microcontroller. A detailed explanation of the protocol and demodulator design, as well as third-party C source code that was used as a starting point, can be found at the following URL: http://swfltek.com/avr/SAME/

In the SAME AFSK protocol, bits are transmitted with a duration of 1.92 milliseconds, and therefore a bit rate of 520.83 bits/second. Logic level zero is represented by three cycles of a 1562.5 Hz audio tone, and logic level one is represented by four cycles of a 2083.3 Hz audio tone. A 16-byte preamble is sent at the beginning of a transmission to allow the receiver to easily find the boundaries between bits before data transmission begins.

Although the demodulator was originally implemented on an ATmega328P device running at a clock frequency of 16 MHz, it could be easily adapted to other AVR® devices. The timer/counter and ADC on the device are set up to sample the incoming audio signal at four times the logic level zero frequency and three times the logic level one frequency, or 6250 Hz. This means that there are (16 MHz/6250 Hz) = 2560 CPU cycles available to process each ADC sample. A block diagram of the demodulator is provided in the figure below.

Figure 1. Demodulator Block Diagram

Each time a new ADC sample is received, it is added to a circular buffer of the most recent 12 ADC samples. Two digital Goertzel bandpass filters, one centered on the logic level zero frequency and the other centered on the logic level one frequency, are then run on the most recent 12 ADC samples, followed by an output magnitude calculation for each filter. The output magnitudes of the two filters are compared to determine whether the received signal represents a logic level zero or logic level one. Some additional processing is performed to find the bit transitions of the preamble and synchronize to them. After synchronization is achieved, demodulated ASCII characters are output to a USART.

AVR® core performance was determined by building the C source code using Atmel Studio 7.0.1645 and running it on an ATmega328P Xplained Mini evaluation kit. Some minor modifications were made to the code to include some calculations for measuring processor utilization, and to make it more tolerant of frequency errors in the transmitter. (The modified code, as well as all code used in the later sections of this document, can be found in the FSK_demod_code_for_AVR_core.zip file associated with this white paper at the Microchip website.) In the worst case, it was found that 749 CPU clock cycles are needed for obtaining and processing an ADC sample. This number includes all the filtering and synchronization operations as well as transmitting demodulated characters out on a USART. Given that there are 2560 CPU cycles per ADC sample, this is a core utilization of (749/2560)*100% = 29.3%.

There are several different ways of interpreting this result. This means that approximately 70% of the AVR® core processing power is still available if it is desired to add additional functionality to the application. Another interpretation is that the CPU clock frequency could be reduced from 16 MHz to 4.8 MHz to reduce power consumption without compromising the functionality of the AFSK demodulator. Yet another interpretation is that the AFSK bit rate, audio frequency, and ADC sample rate parameters could be scaled by a factor of up to 3.4 to achieve bit rates of up to 1.77 kbit/second if the CPU clock remains at 16 MHz.