# AFSK Demodulator with 2x Sampling Rate and Digital Filtering

The AFSK demodulator discussed in the previous section did not have any digital filtering to prevent aliasing of frequencies above half the sample rate (0.5*6250 Hz = 3125 Hz). For example, imagine that there is an interference tone on the incoming analog signal at a frequency of 4687.5 Hz. Because the sampling rate is 6250 Hz, once the 4687.5 Hz analog tone is sampled it would appear in the digital domain at an aliased frequency of (6250-4687.5) Hz = 1562.5 Hz. Since this is the same frequency as the FSK logic level zero signal, it would interfere with the FSK demodulator and prevent it from functioning properly. To prevent this interference, the only option with the previous demodulator code would have been to add a hardware analog filter prior to the ADC input to attenuate signal frequencies above 3125 Hz.

An alternative approach is to sample the analog signal at a higher rate, perform some digital filtering to attenuate frequencies above 3125 Hz, then downsample the signal. The downsampled signal can then be demodulated as before. The AFSK demodulator code described in the previous section was taken as a starting point and then modified to use this approach. A block diagram of this modified demodulator is provided in the figure below.

Figure 1. Demodulator Block Diagram

The modified code uses the ADC to sample the incoming analog signal at 12500 Hz, twice the previous sampling rate of 6250 Hz. The 12500 Hz samples are passed through a 15-tap FIR (Finite Impulse Response) filter that is designed to have greater than 44 dB attenuation beyond a cutoff frequency of 3125 Hz. The FIR filter taps are implemented with 10-bit precision, and the ADC values have 10-bit resolution, so 16-bit by 16-bit multiplication operations are used in the implementation of the FIR filter. The output of the FIR filter is downsampled by a factor of 2 to create a signal at the original sample rate of 6250 Hz, and then this is fed into the original FSK demodulator code designed for a 6250 Hz sample rate.

Consider what happens now with an interfering sine-wave signal at 4687.5 Hz. Because it is sampled at 12500 Hz, it will not be aliased – it will appear at 4687.5 Hz in the sampled version of the signal. Because the FIR filter has greater than 44 dB attenuation at frequencies above 3125 Hz, the interference signal will be reduced to less than 1% of its original amplitude at the output of the FIR filter. After the signal is downsampled to 6250 Hz, aliasing will then occur and the signal will appear at 1562.5 Hz, but it has been reduced in amplitude so much that it will have a negligible effect on the FSK demodulator performance.

Doubling the sample rate to 12500 Hz with a 16 MHz AVR® core clock means that there are now (16 MHz/12500 Hz) = 1280 CPU cycles available per ADC sample. CPU utilization of this code was found to be at most 792 samples per ADC sample, for an AVR® core utilization of (792/1280)*100% = 62%.

As before, this number can be interpreted in various ways. It means that 38% of the core is still available for adding functionality to the application. Another interpretation is that the CPU clock frequency can be reduced from 16 MHz to 10 MHz without compromising the demodulator performance. Yet another interpretation is that the AFSK bit rate, audio frequency, and ADC sample rate parameters could be scaled by a factor of up to 1.6 to achieve FSK bit rates of up to 833 bit/second if the CPU clock remains at 16 MHz.