The application code was further modified to demodulate a more challenging FSK signal – still with a bit duration of 1.92 milliseconds, but with near-ultrasonic frequencies of 16666.7 Hz for logic level one and 17187.5 Hz for logic level zero. This corresponds to exactly 32 or 33 cycles of a sine-wave during the 1.92 millisecond bit interval.

For this application, the timer/counter and ADC on the device are set up to sample the analog signal at a frequency of 50 kHz. A block diagram of this demodulator is provided in the figure below.

Figure 1. Demodulator Block Diagram

An interrupt service routine saves incoming ADC samples in a circular buffer so that they can be processed by a main processing loop. In the main processing loop, the 50 kHz samples are passed through a 9-tap FIR filter that is designed to have greater than 40 dB attenuation below 10 kHz so that typical human voice frequencies are removed from the signal. The FIR filter taps are implemented with 10-bit precision, and the ADC values have 10-bit resolution, so 16-bit by 16-bit multiplication operations are used in the implementation of the FIR filter.

The output of the FIR filter is downsampled by a factor of 8 to result in a signal sampled at 6250 Hz. The near-ultrasonic frequencies of 16666.7 Hz and 17187.5 Hz are aliased to (3*6250 – 16666.7) Hz and (3*6250 – 17187.5) Hz, or 2083.3 Hz and 1562.5 Hz in the downsampled signal, respectively. This means that the original FSK demodulator code can still be used from this point onward.

Given that the core is running at 16 MHz, this means that there are 320 CPU cycles per 50 kHz ADC sample interval and 2560 CPU cycles per 6250 Hz downsample interval. Processor utilization was determined to be as follows:

- Interrupt service routine: 65 cycles per 50 kHz sample = (65/320)*100% = 20.3% CPU utilization
- 9-tap FIR filter & overhead: 468 cycles per 6250 Hz downsample = (468/2560)*100% = 18.3% CPU utilization
- FSK demodulator (including USART sending): 718 cycles per 6250 Hz downsample = (718/2560)*100% = 28.0% CPU utilization

Total CPU utilization is then 20.3% + 18.3% + 28.0% = 66.6%, so about one-third of the CPU is still available for other processing if desired. Alternatively, the processor clock could be reduced from 16 MHz to 10.7 MHz without affecting the demodulator. If the processor clock remains at 16 MHz, FSK bit rates and frequencies could be scaled proportionally by a factor of up to 1.5.