ADC Clock and Conversion Timing

The ADC can prescale the system clock to provide an ADC clock that is between 50 kHz and 200 kHz to get maximum resolution. If an ADC resolution less than 10 bits is required, the ADC clock frequency can be higher than 200 kHz, but it is not recommended to use an ADC clock with a frequency higher than 1 MHz. At 1 MHz we can expect maximum 8 bits of resolution.

The prescaler value is selected by writing the ADC Prescaler Select bit group in the ADC Control and Status A register (ADCSRA.ADPS) accordingly. When initiating a single-ended conversion by writing the ADC Start Conversion bit in ADCSRA (ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle.

The first conversion after the ADC is enabled (ADCSRA.ADEN=1) takes 25 ADC clock cycles in order to initialize the analog circuitry. Then, for further conversions, it takes 13 ADC clock cycles (13.5 for Auto triggered conversions). When bandgap voltage is used as input to ADC it will take a certain time for the voltage to stabilize. The start-up time for the bandgap reference voltage is available in the data sheet section System and reset characteristics.