49.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	PDMC_CR	31:24
		23:16
		15:8
		7:0								SWRST
0x04	PDMC_MR	31:24	CHUNK[3:0]				SINC_OSR[3:0]
		23:16	SINCORDER[3:0]						OSR[1:0]
		15:8
		7:0					PDMCEN3	PDMCEN2	PDMCEN1	PDMCEN0
0x08	PDMC_CFGR	31:24
		23:16		PDMSEL3		PDMSEL2		PDMSEL1		PDMSEL0
		15:8
		7:0		BSSEL3		BSSEL2		BSSEL1		BSSEL0
0x0C	PDMC_RHR	31:24	CHANNEL[7:0]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x10 ... 0x13	Reserved
0x14	PDMC_IER	31:24				WPERR
		23:16
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x18	PDMC_IDR	31:24				WPERR
		23:16
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x1C	PDMC_IMR	31:24				WPERR
		23:16
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x20	PDMC_ISR	31:24				WPERR
		23:16
		15:8
		7:0			RXOVR	RXUDR	RXCHUNK	RXFULL	RXEMPTY	RXRDY
0x24 ... 0x2B	Reserved
0x2C	PDMC_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0							WPITEN	WPEN
0x30	PDMC_WPSR	31:24
		23:16	WPSRC[15:8]
		15:8	WPSRC[7:0]
		7:0						SEQE		WPVS