64.4 Signal Description
| Pin Name | Pin Description | Type |
|---|---|---|
| QSCK | Serial clock | Output |
| MOSI (QIO0)123 | Data output (data input/output 0) | Output (input/output) |
| MISO (QIO1)123 | Data input (data input/output 1) | Input (input/output) |
| QIO23 | Data input/output 2 | Input/output |
| QIO33 | Data input/output 3 | Input/output |
| QIO44 | Data input/output 4 | Input/output |
| QIO54 | Data input/output 5 | Input/output |
| QIO64 | Data input/output 6 | Input/output |
| QIO74 | Data input/output 7 | Input/output |
QCS |
Peripheral chip select | Output |
| QINT | Optional. Interrupt output of an external memory device. Set to 0 if not used. | Input |
| QDQS5678 | Data strobe (input for read accesses, output for write accesses) | Input |
Note:
- MOSI and MISO are used for Single-bit SPI operation.
- QIO0–QIO1 are used for Dual SPI operation.
- QIO0–QIO3 are used for Quad SPI operation.
- QIO4–QIO7 are used for Octal SPI operation.
- QDQS is supplied by most Octal SPI memories.
- Pre-cycle is not supported on the QDQS signal.
- Preamble bits are not supported on the QDQS signal.
- OCTAL SDR with DQS is not supported (QSPI_IFR.DDREN=0, QSPI_IFR.WIDTH=OCT_OUTPUT/OCT_IO/OCT_CMD, QSPI_IFR.DQSEN=1).