34.2 Embedded Characteristics

The Clock Generator is made up of:

  • Oscillators
    • A low-power 32.768 kHz oscillator supporting crystals and resonators (referred to as “32.768 KHz crystal oscillator” throughout the document)
    • An embedded always-on, slow RC oscillator generating a typical 32 kHz clock
    • A 12 to 50 MHz oscillator supporting crystals, resonators and Bypass mode (referred to as “main crystal oscillator” throughout the document)
    • A main RC oscillator generating a typical 12 MHz clock
  • A set of 7 fractional-N PLLs with an input frequency range of 12 to 50 MHz and an internal frequency range of 600 to 1200 MHz, namely:
    • CPUPLL - PLL ID0
    • SYSPLL - PLL ID1
    • DDRPLL - PLL ID2
    • IMGPLL - PLL ID3
    • BAUDPLL - PLL ID4
    • AUDIOPLL - PLL ID5
    • ETHPLL - PLL ID6

The Clock Generator provides the following clocks:

  • MD_SLCK—Monitoring domain slow clock. This clock, sourced from the always-on slow RC oscillator only, is the only permanent clock of the system and feeds safety-critical functions of the device (WDT, RSTC, SCKC, frequency monitors and detectors, PMC start-up time counters).
  • TD_SLCK—Timing domain slow clock. This clock, sourced from the 32.768 kHz crystal oscillator or the always-on slow RC oscillator, is routed to the RTC and RTT peripherals.
  • MAINCK—Output of the main clock oscillator selection. This clock is either the main crystal oscillator or the main RC oscillator.
  • PLL Clocks—Outputs of embedded PLLs