3.5.1 I/O Pin Characteristics

Some clarifications have been made to the I/O Pin Characteristics table. Note that one footnote has been deleted.

Table 39-7. I/O Pin Characteristics(1)
Symbol Description Min. Typ. Max. Units Conditions
Input Low Voltage
VIL I/O PORT:
  • With Schmitt Trigger buffer
0.2×VDD V
  • With I2C levels
0.3×VDD V
  • With SMBus 3.0 levels
0.8 V
RESET Pin 0.2×VDD V
TTL level 0.8 V
Input High Voltage
VIH I/O PORT:
  • With Schmitt Trigger buffer
0.8×VDD V
  • With I2C levels
0.7×VDD V
  • With SMBus 3.0 levels
1.35 V
RESET Pin 0.8×VDD V
TTL level 1.6 V
Input Leakage Current(2)
IIL I/O PORTS(3) <5 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 85°C

<5 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 125°C

RESET Pin(4) ±50 nA GND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 85°C

Pull-up Current
IPUR 140 μA VDD = 3.0V, VPIN = GND
Output Low Voltage
VOL Standard I/O Ports 0.6 V IOL = 10 mA, VDD = 3.0V
Output High Voltage
VOH Standard I/O Ports VDD-0.7 V IOH = 6 mA, VDD = 3.0V
I/O Slew Rate
tSR Rising slew rate 22 ns PORTCTRL.SRL = 0x00
Rising slew rate 45 ns PORTCTRL.SRL = 0x01
Falling slew rate 30 ns PORTCTRL.SRL = 0x01
Falling slew rate 16 ns PORTCTRL.SRL = 0x00
Pin Capacitance
CIO OPAMP output 9 pF
VREFpin 7 pF
XTAL pins 4 pF
Other pins 4 pF

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. These figures are valid for all I/O ports regardless of if they are connected to the VDD or VDDIO2 power domain.
  2. The negative current is defined as the current sourced by the pin.
  3. The leakage current numbers for I/O PORTS are valid also when the pin is used as an input to an enabled analog peripheral.
  4. The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.