2 ADC2 Computation Modes

Basic: In this mode, the ADC conversion can be manually triggered by the core or auto-triggered by other peripherals and external sources. The accumulator logic is not active in Basic mode, which means that the Accumulator (ADACC) and Count (ADCNT) register values are not used throughout the operation, and the Result register (ADRES) will hold the sampled ADC result. Threshold error comparison, double sampling, Continuous mode, and all CVD (Capacitive Voltage Divider) features are still available, but no feature involving the digital filter or average features are used.

Accumulate: In this mode, with each trigger, the ADC conversion result is added to the accumulator and ADCNT increments indicate the number of samples accumulated. The ADCNT value saturates at 255 samples and does not rollover to zero. If the ADACC register overflows, the Accumulator Overflow bit (ADAOV) of the Status register (ADSTAT) will be set. ADCNT and ADACC registers need to be cleared by software once ADCNT reaches the desired number of samples to get the correct average of accumulated ADC samples. The accumulated value can be right-shifted up to six times (by the CPU) by configuring the value of the ADC Accumulate Calculation Right Shift Select bits (ADCRS) of the ADCON2 register. This means that the accumulated value is effectively divided by 2^ADCRS after each conversion. The result of the shifted accumulated value is stored in the ADFLTR register. The code below is an example of how to calculate the average value of ADC samples using the Accumulate mode if the number of samples to be accumulated is 32:

if(ADC_conversion_result_ready)
{
   if(ADCNT>=32)
   {
     read_average_result = ADCC_GetFilterValue();  //ADCRS needs to be configured to 5 in ADC_init
     ADCC_ClearAccumulator(); // will clear ADACC and ADCNT
   }
}

As the filtered value is available after each ADC conversion, and its value is accumulated value divided by 32 (right shifted by five positions). Because of that, the average value at the 32, 64, 96… sample will be the correct expected average value. At this point the ADACC register value is the sum of 32 samples, so after dividing it by 32, an average value can be obtained (division which means right shifting is done by CPU automatically so you need to read the ADFLTR value only). All the other ADFLTR values can be ignored. After the 32^nd sample the accumulator needs to be cleared which will clear the value of the ADACC register and ADCNT.

Average: This mode is like the Accumulate mode, where the ADACC accumulates the data sample and the ADCNT increments with each sample, except that the number of samples being accumulated is up to the value configured in the ADC Repeat Setting Register (ADRPT). When the ADCNT is equal to ADRPT, the value stored in the ADC Filter register (ADFLTR) is the average value of the input signal (ADFLTR=ADACC/2^ADCRS). When the ADCNT exceeds the value of ADRPT, the ADCNT and ADACC registers reset automatically by the CPU to accumulate the data samples again. If the Threshold Interrupt Mode Select bits (ADTMD[2:0] =7 in ADCON3 register) are configured to Interrupt regardless of threshold test result then the ADTIF flag will be set after accumulating samples configured in ADRPT.

Burst Average: This mode works like the Average mode, except that instead of software re-enabling the conversion, the CPU continuously retriggers the ADC conversion until the ADCNT value is equal to the ADRPT value. In other words, with single ADC conversion trigger, all the data samples are accumulated up to the configured ADRPT and when the ADCNT matches the set ADPRT value, the average value of the input signal is attained by reading the ADFLTR value as ADFLTR=ADACC /2^ADCCRS. At the trigger, the accumulator ADACC and ADCNT are automatically cleared by the CPU.

Low-Pass Filter (LPF): This mode is similar to the Average mode but instead of a simple average, it performs a low-pass filter operation on all the samples, passes signals with frequencies below its cutoff, and attenuates frequencies above its cutoff. The ADCRS bits determine the cut-off frequency of the low-pass filter.

AN2801

2 ADC² Computation Modes