3.2.4 DDR Controller and DDR3L Memory Device

The SDRAM memory interface consists of the Universal DDR Memory Controller (UDDRC) and the physical layer interface (DDR3PHY). The UDDRC receives transactions from the internal buses. These transactions are queued internally and scheduled for access to the DDR-SDRAM while satisfying the DDR-SDRAM protocol timing requirements, transaction priorities and dependencies between transactions.

One embedded DDR3L memory (8 Gbit ETRON memory EM6HF16EBXC-12SH) is used as the main system memory, totaling 1 GByte of SDRAM on the board. The memory bus is 16 bits wide and operates at a frequency of up to 533 MHz.

Figure 3-14. Processor MPDDRC Controller

The DDR_VREF pin serves as a voltage reference input for the DDR I/Os when DDR or LPDDR external SDRAM memories are used.

Figure 3-15. DDR3L SDRAM Device