3.2.6 PIO Branching Structure

Most PIO lines share multiple functions and are branched to multiple destinations through passive resistors on the SAMA7D65 Curiosity Pro board.

CAUTION: To ensure flexibility during evaluation and to avoid excluding any options prematurely, all resistors are installed during board manufacturing. It is the end customer's responsibility to ensure that their implementation and connections do not cause functional conflicts, for example, if multiple branches are driven by more than one target device at a time. See the illustration for the PIOA17/FLEXCOM4_IO1 net in the figure below.

Figure 3-16. PIO Branching Example

In the above example, FLEXCOM4_IO1 collects MISO signals coming from five different sources.

In some application-specific contexts, such "MISO" lines can even be connected to signals other than an SPI MISO net. This is especially common for signals originating from extension connectors such as mikroBUS, M.2 and RPi.

As five connected devices cannot drive the line at the same time, some arbitration is required. The user must ensure that the software application manages the situation correctly by enabling only one device at a time or setting up the system hardware to prevent conflicts. This can be achieved by disconnecting some of the devices on the line at the other end or by unsoldering some of the resistors (R79, R80, R81, R82, R330 in this example).

The schematic and tables below summarize the overall PIO branching structure on the SAMA7D65 Curiosity Pro board to help visualize the connections and resistors present on each PIO path.

Figure 3-17. PIO Branching Structure

Table 3-4 provides a summary of the SAMA7D65 PIO lines with resistors on the path to their end destination branches. Note that:

Empty cells (-) in the two leftmost columns indicate that one SAM PIO/signal is directed to multiple end destinations.
Example: PB15 connects to three destinations via three intermediary resistors.
Empty cells (-) in the two rightmost columns indicate that the SAM PIO/signal connects directly, without an intermediary resistor, to the end destination.
Example: PA00/NAND0_0.NAND_WE and PA01/NAND0_0.NAND_ALE connect directly to the NAND Flash device.

Table 3-4. PIO Lines from SAMA7D65 to End Destination Branches with Resistors on the Path
PIO Line	Net at SAMA7D65 Pin	Resistor	Net after the Resistor
PA00	NAND0_0.NAND_WE	–	–
PA01	NAND0_0.NAND_ALE	–	–
PA02	NAND0_0.NAND_CLE	–	–
PA03	NAND0_0.NAND_DAT0	–	–
PA04	NAND0_0.NAND_DAT1	–	–
PA05	NAND0_0.NAND_DAT4	–	–
PA06	NAND0_0.NAND_DAT5	–	–
PA07	NAND0_0.NAND_DAT6	–	–
PA08	NAND0_0.NAND_DAT7	–	–
PA09	NAND0_0.NAND_DAT2	–	–
PA10	NAND0_0.NAND_DAT3	–	–
PA11	NAND0_0.NAND_RDY	–	–
PA12	NAND0_0.NAND_OE	–	–
PA13	NAND0_0.NAND_CS	–	–
PA14	FLEXCOM4_IO4	R110¹	USBIO-C_A_0.CS
–	–	R91	MBUS1_0.MBUS_CS
PA15	FLEXCOM4_IO3	R89	MBUS0_0.MBUS_CS
PA16	FLEXCOM4_IO2	R331	USBIO-C_A_0.SCK
–	–	R84	MBUS0_0.MBUS_SCK
–	–	R85	MBUS1_0.MBUS_SCK
–	–	R86	RPI0_0.SCK
–	–	R87	GMAC0_0.SCK
PA17	FLEXCOM4_IO1	R330	USBIO-C_A_0.MISO
–	–	R79	MBUS0_0.MBUS_MISO
–	–	R80	MBUS1_0.MBUS_MISO
–	–	R81	RPI0_0.MISO
–	–	R82	GMAC0_0.MISO
PA18	PA18	R31	FLEXCOM4_IO0
PA19	PA19	R33	FLEXCOM4_IO5
PA20	FLEXCOM4_IO6	R96	RPI0_0.NPCS1
–	–	R97	GMAC0_0.CS
PA21	USER_IO0_0.LED_BLUE	–	–
PA22	MBUS1_0.MBUS_INT	–	–
PA23	RPI0_0.RXD	–	–
PA24	RPI0_0.TXD	–	–
PA25	GMAC0_0.TXEN	–	–
PA26	GMAC0_0.TX0	–	–
PA27	GMAC0_0.TX1	–	–
PA28	GMAC0_0.RXCTL	–	–
PA29	GMAC0_0.RX0	–	–
PA30	GMAC0_0.RX1	–	–
PA31	GMAC0_0.MDC	–	–
PB00	GMAC0_0.MDIO	–	–
PB01	GMAC0_0.TXCK	–	–
PB02	GMAC0_0.RX2	–	–
PB03	GMAC0_0.RXCK	–	–
PB04	GMAC0_0.TX2	–	–
PB05	GMAC0_0.TX3	–	–
PB06	GMAC0_0.RX3	–	–
PB07	MBUS0_0.MBUS_INT	–	–
PB08	QSPI0_0.QSPI0_IO3	–	–
PB09	QSPI0_0.QSPI0_IO2	–	–
PB10	QSPI0_0.QSPI0_IO1	–	–
PB11	QSPI0_0.QSPI0_IO0	–	–
PB12	QSPI0_0.QSPI0_CS	–	–
PB13	QSPI0_0.QSPI0_SCK	–	–
PB14	PB14	R35	MIPI_IO0_0.MIPI_PWM
–	–	R36	LVDS_IO0_0.LVDS_PWM
PB15	PB15	R45	USER_IO0_0.LED_GREEN
–	–	R46	MBUS0_0.MBUS_PWM
–	–	R47	RPI0_0.PWM0
PB16	PB16	R38	MIPI_IO0_0.MIPI_IRQ
–	–	R39	LVDS_IO0_0.LVDS_IRQ
–	–	R40	RPI0_0.GPIO16
PB17	PB17	R48	USER_IO0_0.LED_RED
–	–	R49	MBUS1_0.MBUS_PWM
–	–	R50	RPI0_0.PWM1
PB18	PB18	R42	MIPI_IO0_0.MIPI_ENABLE
–	–	R43	LVDS_IO0_0.LVDS_ENABLE
PB19	FLEXCOM10_IO1	R100	PMIC_0.TWCK
–	–	R101	PAC19340_0.TWCK0
–	–	R103	EEPROM0_0.TWCK
–	–	R104	GMAC0_0.TWCK
PB20	FLEXCOM10_IO0	R106	PMIC_0.TWD
–	–	R107	PAC19340_0.TWD0
–	–	R108	EEPROM0_0.TWD
–	–	R109	GMAC0_0.TWD
PB21	USBIO-C_A_0.INT_N	–	–
PB22	SDMMC1_0.SDMMC_CMD	–	–
PB23	SDMMC1_0.SDMMC_CLK	–	–
PB24	SDMMC1_0.SDMMC_DATA0	–	–
PB25	SDMMC1_0.SDMMC_DATA1	–	–
PB26	SDMMC1_0.SDMMC_DATA2	–	–
PB27	SDMMC1_0.SDMMC_DATA3	–	–
PB28	USBIO-C_A_0.EN	–	–
PB29	SDMMC1_0.SDMMC_CD	–	–
PB30	SDMMC1_0.SDMMC_1V8SEL	–	–
PB31	PB31	R61	PAC19340_0.nINT
–	–	R62	RPI0_0.GPCLK0
–	–	R63	USBIO-C_A_0.CC1
PC00	PC0	R64	RPI0_0.GPCLK2
–	–	R65	USBIO-C_A_0.CC2
PC01	GMAC0_0.INT	–	–
PC02	PMIC_0.nINT	–	–
PC03	RPI0_0.GPIO17	–	–
PC04	RPI0_0.GPIO27	–	–
PC05	MBUS0_0.MBUS_AN	–	–
PC06	FLEXCOM0_IO1	R113	LVDS_IO0_0.LVDS_TWCK
–	–	R114	MIPI_IO0_0.MIPI_TWCK
–	–	R115	MBUS0_0.MBUS_TWCK
–	–	R116	MBUS1_0.MBUS_TWCK
–	–	R118	RPI0_0.TWCK
–	–	R119	M2_WIFI_IO0_0.M2_WIFI_TWCK
PC07	FLEXCOM0_IO0	R123	LVDS_IO0_0.LVDS_TWD
–	–	R124	MIPI_IO0_0.MIPI_TWD
–	–	R125	MBUS0_0.MBUS_TWD
–	–	R126	MBUS1_0.MBUS_TWD
–	–	R127	RPI0_0.TWD
–	–	R128	M2_WIFI_IO0_0.M2_WIFI_TWD
PC08	USBIO-C_A_0.VBDET	R2	USBA_VBUS_5V
PC09	PC9	R72	MBUS0_0.MBUS_nRST
–	–	R73	MBUS1_0.MBUS_nRST
PC10	USER_IO0_0.USER_BUTTON	–	–
PC11	RPI0_0.GPIO24	–	–
PC12	RPI0_0.GPIO25	–	–
PC13	MBUS1_0.MBUS_AN	–	–
PC14	RPI0_0.I2S_DIN0	–	–
PC15	RPI0_0.I2S_WS	–	–
PC16	RPI0_0.I2S_CK	–	–
PC17	RPI0_0.I2S_DOUT0	–	–
PC18	PC18	R57	USBIO_B_0.USBIO_OC
–	–	R58	USBIO_C_0.USBIO_OC
PC19	PC19	R59	USBIO-C_A_0.OC
–	–	R60	RPI0_0.GPIO26
PC20	USBIO_B_0.USBIO_EN	–	–
PC21	USBIO_C_0.USBIO_EN	–	–
PC22	JTAG0_0.JTAG_NRST	–	–
PC23	JTAG0_0.JTAG_TCK	–	–
PC24	JTAG0_0.JTAG_TMS	–	–
PC25	JTAG0_0.JTAG_TDI	–	–
PC26	JTAG0_0.JTAG_TDO	–	–
PC27	PC27	R51	SDMMC2_0.SDMMC_CMD
–	–	R52	M2_WIFI_IO0_0.M2_WIFI_MOSI
PC28	PC28	R53	SDMMC2_0.SDMMC_CLK
–	–	R54	M2_WIFI_IO0_0.M2_WIFI_MISO
PC29	PC29	R55	SDMMC2_0.SDMMC_DATA0
–	–	R56	M2_WIFI_IO0_0.M2_WIFI_SCK
PC30	SDMMC2_0.SDMMC_DATA1	–	–
PC31	SDMMC2_0.SDMMC_DATA2	–	–
PD00	SDMMC2_0.SDMMC_DATA3	–	–
PD01	PD1	R66	M2_WIFI_IO0_0.M2_WIFI_IRQ
–	–	R67	RPI0_0.GPIO22
PD02	PD2	R68	M2_WIFI_IO0_0.M2_WIFI_TW_IRQ
–	–	R69	RPI0_0.GPIO23
PD03	M2_BT_IO0_0.M2_BT_RTS	–	–
PD04	M2_WIFI_IO0_0.M2_WIFI_WAKE	–	–
PD05	M2_BT_IO0_0.M2_BT_CTS	–	–
PD06	M2_BT_IO0_0.M2_BT_RX	R149	MODE_SELECT_2
PD07	M2_BT_IO0_0.M2_BT_TX	R150	MODE_SELECT_1
PD08	MBUS0_0.MBUS_TX	–	–
PD09	MBUS0_0.MBUS_RX	–	–
PD10	CAN1_0.CAN_TX	–	–
PD11	CAN1_0.CAN_RX	–	–
PD12	CAN2_0.CAN_TX	–	–
PD13	CAN2_0.CAN_RX	–	–
PD14	CAN3_0.CAN_TX	–	–
PD15	CAN3_0.CAN_RX	–	–
PD16	MBUS1_0.MBUS_TX	–	–
PD17	MBUS1_0.MBUS_RX	–	–
PD18	DBGU0_0.DBGU_TX	–	–
PD19	DBGU0_0.DBGU_RX	–	–
PD20	PD20	R70	M2_WIFI_IO0_0.M2_WIFI_NRST
–	–	R71	RPI0_0.GPCLK1
PD21	GMAC1_0.TXEN	–	–
PD22	GMAC1_0.TX0	–	–
PD23	GMAC1_0.TX1	–	–
PD24	GMAC1_0.RXCTL	–	–
PD25	GMAC1_0.MDC	–	–
PD26	GMAC1_0.MDIO	–	–
PD27	GMAC1_0.RX0	R156	RXD0_R
PD28	GMAC1_0.RX1	R157	RXD1_R
PD29	GMAC1_0.TXCK	R183	CLK_OUT
PD30	GMAC1_0.RX2	R158	RXD2_R
PD31	GMAC1_0.RX3	R159	RXD3_R
PE00	GMAC1_0.TX2	–	–
PE01	GMAC1_0.TX3	–	–
PE02	GMAC1_0.RXCK	R162	RX_CLK_R
PE03	GMAC1_0.INT	–	–
PE04	LVDS0_0.LVDS_D0_N	–	–
PE05	LVDS0_0.LVDS_D0_P	–	–
PE06	LVDS0_0.LVDS_D1_N	–	–
PE07	LVDS0_0.LVDS_D1_P	–	–
PE08	LVDS0_0.LVDS_D2_N	–	–
PE09	LVDS0_0.LVDS_D2_P	–	–
PE10	LVDS0_0.LVDS_D3_N	–	–
PE11	LVDS0_0.LVDS_D3_P	–	–
PE12	LVDS0_0.LVDS_CK_N	–	–
PE13	LVDS0_0.LVDS_CK_P	–	–

Note:

Not populated.