3.4.5 LVDS Display Interface
The Low Voltage Differential Signaling Controller (LVDSC) manages data format conversion from the LCD Controller internal DPI bus to OpenLDI LVDS output signals.
LVDSC functions include bit mapping, balanced mode management and serializer.
On the SAMA7D65 Curiosity Pro, the display is connected to the 30-pin FPC connector (J68).
Four headers (J55, J56, J57, J58) are arranged in a rectangular pattern on the PCB layout. These headers act as "pillars" for mounting a standard display onto the board.
|
PIO |
Signal Name |
Signal Description |
|---|---|---|
|
PB18 |
LVDS_IO0_0.LVDS_ENABLE |
Display enable signal |
|
PB16 |
LVDS_IO0_0.LVDS_IRQ |
Display touchscreen interrupt line |
|
PB14 |
LVDS_IO0_0.LVDS_PWM |
Display PWM signal |
|
PC06 |
LVDS_IO0_0.LVDS_TWCK |
Display TWI clock signal |
|
PC07 |
LVDS_IO0_0.LVDS_TWD |
Display TWI data signal |
|
PE12 |
LVDS0_0.LVDS_CK_N |
LVDS clock (N) |
|
PE13 |
LVDS0_0.LVDS_CK_P |
LVDS clock (P) |
|
PE04 |
LVDS0_0.LVDS_D0_N |
LVDS data 0 (N) |
|
PE05 |
LVDS0_0.LVDS_D0_P |
LVDS data 0 (P) |
|
PE06 |
LVDS0_0.LVDS_D1_N |
LVDS data 1 (N) |
|
PE07 |
LVDS0_0.LVDS_D1_P |
LVDS data 1 (P) |
|
PE08 |
LVDS0_0.LVDS_D2_N |
LVDS data 2 (N) |
|
PE09 |
LVDS0_0.LVDS_D2_P |
LVDS data 2 (P) |
|
PE10 |
LVDS0_0.LVDS_D3_N |
LVDS data 3 (N) |
|
PE11 |
LVDS0_0.LVDS_D3_P |
LVDS data 3 (P) |