PIC32CX SG41/SG60/SG61 Family Data Sheet

10.3.2 Configuration

Figure 10-1. Host-Client Relations High-Speed Bus Matrix

Table 10-1. High Speed Bus Matrix Hosts
High-Speed Bus Matrix Hosts	Host ID
CM4S - Cortex-M4 Processor	0
CMCC - Cortex-M Cache Controller (Cortex-M4F ICode and DCode Interfaces)	1
DMAC - Direct Memory Access Controller/Data Write Access	4
DMAC - Direct Memory Access Controller/Data Read Access	5
ICM - Integrity Check Monitor	6
DSU - Device Service Unit	7

Table 10-2. High-Speed Bus Matrix Clients
High-Speed Bus Matrix Clients	Client ID
Internal Flash Memory	0, 1
Smart EEPROM	2
SRAM Port 0 - CM4 Access	3
SRAM Port 1 - DSU Access	4
SRAM Port 2 - DMAC Data-Write Access	5
SRAM Port 3 - DMAC Data-Read and ICM Access	6
AHB-APB Bridge A	7
AHB-APB Bridge B	8
AHB-APB Bridge C	9
AHB-APB Bridge D	10
PUKCC	11
SDHC0	12
SDHC1	13
QSPI	14
BACKUP RAM Memory	15

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