61 PIC32CX SG41/SG60/SG61 Revision History

Revison J - 07/2025

The following updates were performed in this revision:


Section	Description
1-MB Flash, 256-KB SRAM with optional Hardware Security Module, Crypto, 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC	Added VDDIOB information to Operating Conditions
Pinout and Packaging	Updated the following Pinout tables with new VDDIOB information for the PIC32CX SG41: 64-Pin TQFP 80-Pin WLCSP 100-Pin TFBGA and 100-Pin TQFP 128-pin TQFP
Device Start-Up	Added VDDIOB content to Power-Up Considerations
Electrical Specifications 85°C	Added VDDIOB information to table 55-2 in General Operating Ratings and Thermal Conditions Added VDDIOB information to REG_43, REG_44, and a new Entry for REG_54 to Power Supply, along with the addition of supporting notes
Schematic Checklist	Added VDDIOB information to the Bulk capacitors description in Decoupling Capacitors Updated all images in Power Supply Connections to reflect the addition of VDDIOB information Updated the table in Power Supply Connections to include a row for VDDIOB, and new notes

Revision H - 05/2025

The following updates were performed in this revision:


Section	Description
1-MB Flash, 256-KB SRAM with optional Hardware Security Module, Crypto, 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC	Updated Table with new 80-pin WLCSP information
Configuration Summary	Updated Table 1-1 with 80-pin WLCSP information
Pinout and Packaging	Added a new Pinout for the 80-pin WLCSP Package
Packaging Information	Added a new 80-pin WLCSP Package Drawings

Revision G - 08/2023

The following updates were performed in this revision:


Section	Description
1-MB Flash, 256-KB SRAM with optional Hardware Security Module, Crypto, 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC	Updated Table
Configuration Summary	Updated Table 1-1
Ordering Information	Added additional package and count options in Figure 2-1
Pinout and Packaging	Added section 64-Pin TQFP Modified PNs in sections 100-Pin TFBGA and 100-Pin TQFP and 128-pin TQFP Added info of 64-pin TQFP in Table 4-31
Device Service Unit (DSU)	Updated the table for the DEVSEL bitfield in the DID Register
SERCOM Inter-Integrated Circuit (SERCOM I²C)	Added info of 64-pin TQFP in Table 34-1
Electrical Specifications 85°C	Added info of 64-pin TQFP in Thermal Packaging Characteristics (PIC32CX SG41)
Packaging Information	Added Figure 57-1 Added section 64-pin TQFP

Revision F - 05/2023

The following updates were performed in this revision:


Section	Description
1-MB Flash, 256-KB SRAM with optional Hardware Security Module, Crypto, 1 MSPS 12-bit ADC, QSPI, USB, Ethernet, and PTC	Added a new section titled: Software and Tools Support: Develop Prototypes Quickly With A Powerful, Easy-to-Use Ecosystem
NVMCTRL	Updated the settings in Security Bit Set Procedure Updated the Register reset value for SEESTAT Updated Security Bit Set Procedure, Replaced Step no. 3 Replace note Immutable Boot, Boot Read Protection, and Secure Debug Features Overview, under the table 27-13
CAN	Added new verbiage to the NBTP Register
RTC	Updated Timestamp with a new note, and added Note 3.
CCL	Updated important note in Enabling, Disabling, and Resetting, also updated the CTRL register
ADC	A new note has been added Host - Client Operation
AC	A note has been added Offset Compensation
USB	Performed minor editorial updates to FSMSTATUS Updated the table for the SPDCONF bitfield and removed obsolete bitfields from the CTRLB Register Removed obsolete bitfield MFNUM from the FNUM Register Removed obsolete bitfield MSOF from the following registers: INTENCLR INTENSET INTFLAG Removed obsolete bitfield NYETDIS from the EPCFGn Register Removed the TSTK and TSTJ obsolete bitfields from the CTRLB Register and updated the SPDCONF bitfield table Removed an obsolete table form the FLENCE bitfield in the HSOFC Register Performed minor editorial updates to STATUS Removed obsolete bitfield MFNUM from the FNUM Register Updated the table for the FLENHIGH bitfield in the FLENHIGH Register Removed an obsolete table from the BINTERVAL bitfield in the BINTERVALn Register Updated the table for the SIZE bitfield in the PCKSIZE Register

Revision E - 02/2023

The following updates were performed in this revision:


Section	Description
Block Diagram	Replaced the diagram with a new image
Processor and Architecture	Clarified CMCC in table 10-1 in Configuration
DSU	Updated the PROT bitfield in the STATUSB Register with new verbiage
NVMCTRL	Clarified verbiage following Table 27-2 in Memory Organization Added new verbiage to line items 1 and 3, and added new line item 4 in Security Bit Set Procedure Updated bit names and instructions for setting the Hard lock in Chip Erase Hard Lock Updated the notes with new verbiage in Boot Protect Hard Lock Removed erroneous text and updated all tables in Immutable Boot, Boot Read Protection and Secure Debug Features Overview Updated the table for the PSZ bitfield in the PARAM Register Updated bitfield resets in the SEESTAT Register
SERCOM USART	Clarified verbiage in Data Transmission Added a new note to Lin Host Added a note to the HDRDLY and BRKLEN bitfields of the CTRLC Register
TC	Added a new line item 4 to the note in Capture Operations
ADC	Added a new section Rail-to-Rail Operation
Electrical Specifications	Updated Min specifications in the I²S Host Mode Electrical Specifications table Modified figure 55-15 in CAN Electrical Specifications to remove an erroneous function
Electrical Specifications at 125°C	Modified figure 56-10 in CAN Electrical Specifications to remove an erroneous function
Packaging Information	Removed obsolete Specification tables from the following packages: 100-pin TQFP (E5X) 100-pin TQFP (with exposed pad) 100-pin TFBGA 128-pin TQFP 128-pin TQFP (with exposed pad)

Revision D - 11/2022

The following updates were performed in this revision:


Section	Description
Pinout and Packaging	Updated values for the ANAREF, CCL, EIC, GMAC, ADC, and the GCLK for the following Pinout tables: 100-pin TFBGA/100-pin TQFP I/O PINMUX 128-pin TQFP I/O PINMUX (PIC32CX SG41) 128-pin TQFP I/O PINMUX (PIC32CX SG60/SG61)
DMAC	Updated the CRCSRC Bitfield of the CRCCTRL register with new channel naming
SERCOM SPI	Added new text for Host and Client mode to the DOPO Bitfield of the CTRLA register
USB	Updated the PCKSIZE register with new Bitfield information for the BYTE_COUNT Bitfield
Electrical Specifications	Replaced and added new tables in the following sections: MCU Active Current Consumption MCU Idle Power MCU Standby Current Consumption MCU Hibernate Current Consumption MCU Backup Current Consumption MCU Off Current Consumption Peripheral Active Current AC Electrical Specifications I²S Electrical Specifications QSPI Electrical Specifications Updated the tables in the following sections with new temperature and voltage specifications in the table headings and new minimum/maximum specifications: Wake-Up Timings Electrical Specifications I/O Pin Electrical Specifications Internal Voltage Reference Electrical Specifications Maximum Clock Frequencies Electrical Specifications XOSC Maximum Clock Frequencies Electrical Specifications XOSC32K Electrical Specifications OSCULP32K Electrical Specifications DFLL48M Electrical Specifications FDPLL200M Electrical Specifications DAC Module Electrical Specifications ADC Electrical Specifications PTC Electrical Specifications SPI Electrical Specifications USART Electrical Specifications I²C Electrical Specifications QSPI Electrical Specifications CAN Electrical Specifications TC Electrical Specifications TCC Electrical Specifications USB Electrical Specifications PCC Electrical Specifications NVM Block (Flash, Data Flash, NVM Configuration Rows) Electrical Specifications EEPROM Electrical Specifications GMAC Electrical Specifications FREQM Electrical Specifications TRNG Electrical Specifications PDEC Electrical Specifications SDHC Electrical Specifications SWD 2-Wire Electrical Specifications Replaced the figure for SPI Host Module (CPHA=0) Timing Diagrams in SPI Electrical Specifications
Electrical Specifications at 125°C	New chapter added in this revision
Schematic Checklist	Updated the Introduction with references to other documents Updated External Reset Circuit with a new image for Figure 58-7, and added new text. Removed obsolete diagrams. Updated the text in USB Interface and removed obsolete diagrams

Revision C - 08/2022

The following updates were performed in this revision:


Section	Description
Pinout and Packaging	Updated the note in the Supply Controller Pinout Added a new section called Backup I/O Pins
Signal Descriptions List	Updated the listings for the VBAT to include the associated pad name
Memories	Updated the table in NVM Configuration Rows to properly display abbreviations Updated the table in NVM User Row (UROW) to display new default values for bits 0 - 14 Updated the titles to display proper abbreviations for: NVM Boot Configuration Row (BOCOR) NVM Software Calibration Area Row (SW0)
GCLK	Updated the SWRST bit of the CTRLA Register with new notes
OSC32KCTRL	Removed erroneous notes about disabling the Clock Failure Detector from Clock Failure Detection Operation
OSCCTRL	Removed erroneous notes about disabling the Clock Failure Detector from Clock Failure Detection Operation Added a note to USB Clock Recovery Mode in Additional Features
SUPC	Added the proper pad name to VBAT in Features Added the proper pad name to VBAT in the Block Diagram Added a new note to Signal Description Retitled the section Output Pins from backup Output Pins and added a new paragraph Updated the wording of the first paragraph in Enabling, Disabling, and Resetting Updated the BKOUT Register to remove the word Backup from the descriptions in the bitfields Updated the BKIN Register to remove the word Backup from the descriptions in the bitfields
RTC	Updated the OUT Signal in the Signal Description to remove erroneous bit definitions Updated the naming of the OUT Register in Tamper Detection and Active Layer Protection Added new notes to the SWRST bit for the following registers: Mode 0-32 Bit Counter CTRLA Mode 1-16 Bit Counter CTRLA Mode 2 - Clock/Calendar CTRLA
FREQM	Updated the SWRST bit of the CTRLA Register with new notes
EIC	Removed an erroneous note from Initialization Removed an erroneous note from Asynchronous Edge Detection Mode (No Debouncing) Updated the SWRST bit of the CTRLA Register with new notes, and removed an erroneous note from the ENABLE bit
NVMCTRL	Added a new section of text to Writing and Reading the SmartEEPROM Updated the definitions for the SEEWRC bit in the INTFLAG Register Updated the table for the WMODE bit in the SEECFG Register
PORT	Removed erroneous text from the Overview PORT Access Priority was rewritten to remove obsolete data
SERCOM USART	Minor rewording of terminology in Start-of-Frame Detection Updated the SWRST bit of the CTRLA Register with new notes
SERCOM SPI	Added new text to I/O Lines to define registers and bitfields Updated the SWRST bit of the CTRLA Register with new notes
SERCOM I²C	Updated the SWRST bit of the Client CTRLA Register with new notes Updated the SWRST bit of the Host CTRLA Register with new notes
CAN	Added new text to the Signal Description Updates bit 8-6 to display Reserved in Standard Message ID Filter Element
PCC	Updated the Block Diagram with new bits for DATA Updated the Signal Description with new bits for DATA Added in new content for the MCLK APB Clock in Peripheral Dependencies Updated the Principle of Operation with new bits for DATA in Figure 39-2
USB	Updated the SWRST bit of the Communication Device Host CTRLA Register with new notes
PDEC	Updated the SWRST bit of the CTRLA Register with new notes
TC	Updated the SWRST bit with new notes in the following registers: 8-bit Mode CTRLA 16-bit Mode CTRLA 32-bit Mode CTRLA Replaced the text for the CMD bitfield for the following registers: 8-bit CTRLBCLR 16-bit CTRLBCLR 32-bit CTRLBCLR 8-bit CTRLBSET 16-bit CTRLBSET 32-bit CTRLBSET
TCC	Added a new note to Counter Operation Updated the SWRST bit of the CTRLA Register with new notes Replaced the text for the CMD bitfield in the CTRLBCLR Register Added new information to the CMD and DIR bitfields for the CTRLBSET Register Added a Register property to the STATUS Register, and removed an obsolete note Updated the Register properties in the following registers: WAVE CC PATTBUF PERBUF CCBUF
ADC	Updated the SWRST bit of the CTRLA Register with new notes
AC	Updated DAC to display DAC0 in Features Updated DAC to display DAC0 in the Block Diagram Added a new note to Window Operation Updated the SWRST and ENABLE bits of the CTRLA Register with new notes Added new text to the WSTATE bitfield in the STATUSA Register Renamed the COMPCTRL Register to COMPCTRLn and updated the table definitions for the HYST bitfield
DAC	Updated the SWRST bit of the CTRLA Register with new notes
PIC32CX SG41/SG60/SG61 Electrical Specifications	Updated values for Absolute Maximum Ratings Minor formatting updates in Power Supply Minor formatting updates to the ADC Electrical Specifications table Updated the units for CMP_19 in AC Electrical Specifications Minor updates to the specifications for TCC_15 and TCC_17 in TCC Timer Capture Module Electrical Specifications Added new Min and max values to the SD Host Controller Timing Specifications
Schematic Checklist	Updated the pad name for VBAT in the Power Supply Connections table

Revision B - 01/2022

The following updates were performed in this revision:

Terminology used in this document may not match with the contents of the current revision of the device errata or other Microchip documentation and collateral. If there are any questions or concerns regarding terminology, contact a Microchip Support or Sales Representative.


Section	Description
General	Throughout the document, VDDANA and GNDANA were updated to read AVDD and AVSS respectively Throughout the document, VDDIO and GND were updated to read VDD and VSS respectively The I²C, SPI and I²S standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively. Removed erroneous references to a temperature sensor from the entire document
Features	Updated the specifications for the following subsections: I/O Clock Management System Package Types table
Configuration Summary	Reformatted the entire table and added a Max Frequency column.
Pinout and Packaging	Updated the following packages with several new pin names: 100-pin TFBGA and 100-pin TQFP 128-pin TQFP
Power Supply and Startup Considerations	Updated the Voltage range specifications in Power Supplies. Reworked and restructured the entire chapter
SUPC	Updated the ACTION bit for the BOD33 Register to clarify bit naming.
EIC	Removed erroneous references to another product from: Features Interrupt Pin Debouncing
FREQM	Removed the note from the Block Diagram.
SERCOM SPI	Replaced all _SS with SS Removed duplicate text sections from Transferring Data
HSM	Replaced the content in Overview Clarified the SPI interface in Features Updated the title and removed erroneous text in Application Removed the Block Diagram Added in a new topic, I/O Lines Updated Debug Operation with new text Clarified the text in the Functional Description
TC	Removed references to a different product from Features.
TCC	Updated erroneous references to the TC to read TCC in the EVACT bitfields of the EVCTRL register.
PDEC	Updated the following sections with all new text and images: Position and Rotation Measurement HALL Operation Mode Updated Hall Sensor Control with new bulleted text Updated the Bit naming and numbering for the PINVENx and PINENx bitfields in the CTRLA Register Updated the bit naming and numbering for the MCEOx, EVEIx and the EVINVx bitfields in the EVCTRL Register
AC	Updated COMPCTRLx to COMPCTRLn throughout the entire chapter.
PIC32CX SG41/SG60/SG61 Electrical Specifications	Added Electrical Specifications for the product.
Packaging Information	Updated Figure 54-1 and 54-2 Updated the Device and Package Maximum Weight tables for the following packages: 128-pin TQFP 128-pin TQFP (with exposed pad)
Schematic Checklist	Removed erroneous content from Power Supply Updated Power Supply Connections with all new figures and updated the notes at the end of the section Replaced the text in Special Consideration for Packages with an Exposed Pad Replaced the text, table and figures in External Analog Reference Connections Replaced the text in External Reset Circuit Replaced the text in Unused or Unconnected Pins Updated the content for the Description column for the table in External Clock Source Updated the figure with new C1 and C2 information, and added all new content to the table in Crystal Oscillator Renamed External Real Time Oscillator to 32.768 kHz Crystal Oscillator, replaced the text and table with new content Updated Programming and Debug with all new content Updated the figure in Trace (CoreSight 20) Connector Removed the table and updated the figure in QSPI Interface. Updated the first paragraph in USB Interface Updated the figure in SDHC Interface. Added the following new topics/sections to the Schematic Checklist section: Decoupling Capacitors Debugging or Programming Pins Designing for High-Speed Peripherals

Revision A - 07/2021

This is the initial release of this document.

PIC32CX SG41/SG60/SG61 Family Data Sheet

61 PIC32CX SG41/SG60/SG61 Revision History

Revison J - 07/2025

Revision H - 05/2025

Revision G - 08/2023

Revision F - 05/2023

Revision E - 02/2023

Revision D - 11/2022

Revision C - 08/2022

Revision B - 01/2022

Revision A - 07/2021