49.6.3 Status Register
| Name: | SR |
| Offset: | 0x08 |
| Property: | Read-Only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RMDIS[3:0] | RAWRMDIS[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bits 15:12 – RMDIS[3:0] Region Monitoring Disabled Status
| Value | Description |
|---|---|
| 0 | Region i is being monitored (occurs after integrity check value has been calculated and written to Hash area). |
| 1 | Region i is not being monitored. |
Bits 11:8 – RAWRMDIS[3:0] Region Monitoring Disabled Raw Status
Bit 0 – ENABLE ICM Controller Enable Register
| Value | Description |
|---|---|
| 0 | ICM controller is disabled. |
| 1 | ICM controller is activated. |