3 Pinout and Signal Descriptions

The following table provides details on signal names classified by the peripherals along with the device pinout for the PIC32WM-BW1 Module.

Table 3-1. Pinout and Signal Descriptions List
Pin Number	Module Pin Name	Pin Type	Description	Peripherals
Pin Number	Module Pin Name	Pin Type	Description	AC	ADC	EIC⁽⁴⁾	GPIO ^{(1, 2)}	QSPI	RTCC	SERCOM	OSC	DEBUG
1–4	GND	P	Ground	—	—	—	—	—	—	—	—	—
5	NMCLR	I	PIC32CX-BZ2 IC Reset	—	—	—	—	—	—	—	—	—
6	PB1⁽⁹⁾	I/O	PIC32CX-BZ2 Port B Digital I/O	AC_AIN3	AN5	—	RB1	—	—	—		—
7	PB2	I/O	PIC32CX-BZ2 Port B Digital I/O	AC_AIN0	AN6	—	RB2	—	—	—	—	—
8	PB3	I/O	PIC32CX-BZ2 Port B Digital I/O	AC_AIN1	AN7	—	RB3	—	—	—	—	—
9	PB4	I/O	PIC32CX-BZ2 Port B Digital I/O	—	AN0	INT0⁽⁶⁾	RB4	—	—	—	—	TRACEDATA3
10	PB5	I/O	PIC32CX-BZ2 Port B Digital I/O	—	AN1	—	RB5	—	—	—	—	TRACEDATA0
11	PB6	I/O	PIC32CX-BZ2 Port B Digital I/O	—	ANN0, AN2	—	RB6	—	—	—	—	TRACEDATA1
12	PA11	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA11⁽⁵⁾	—	—	—	SOSCI	—
13	PA12	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA12⁽⁵⁾	—	—	—	SOSCO	—
14	GND	P	Ground	—	—	—	—	—	—	—	—	—
15	PB9	I/O	PIC32CX-BZ2 Port B Digital I/O	—	—	—	RB9	—	—	—	—	CM4_SWDIO
16	PB8	I/O	PIC32CX-BZ2 Port B Digital I/O	—	—	—	RB8	—	—	—	—	CM4_SWCLK
17	PB7	I/O	PIC32CX-BZ2 Port B Digital I/O	LVDIN	AN3	—	RB7	—	—	—	—	TRACEDATA2, CM4_SWO
18	PA4	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA4	—	RTC_OUT	SERCOM0_PAD3	—	—
19	PA3	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA3	—	RTC_IN0	SERCOM0_PAD2	SCLKI	—
20	PA6	I/O	PIC32CX-BZ2 Port A Digital I/O	AC_CMP1_ALT			RA6	—	—	SERCOM0_PAD1	—	—
21	PA5	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA5	—	—	SERCOM0_PAD0	—	—
22	PA2	I/O	PIC32CX-BZ2 Port A Digital I/O	AC_CMP0	—	—	RA2	—	RTC_IN1	—	—	—
23	PA0	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA0	QSPI_DATA2	RTC_IN3	—	—	—
24	PA1	I/O	PIC32CX-BZ2 Port A Digital I/O	AC_CMP1	—	—	RA1	QSPI_DATA3	RTC_IN2	—	—	—
25	PB13	I/O	QSPI_DATA1	—	—	—	—	QSPI_DATA1⁽⁸⁾	RTC_EVENT	—	—	—
26	PB12	I/O	QSPI_DATA0	—	—	—	—	QSPI_DATA0⁽⁸⁾	—	—	—	—
27	PB10	I/O	QSPI_CS	—	—	—	—	QSPI_CS⁽⁸⁾	—	—	—	—
28	GND	P	Ground	—	—	—	—	—	—	—	—	—
29	PB11	I/O	QSPI_CLK	—	—	—	—	QSPI_SCK⁽⁸⁾	—	—	—	—
30	V_DD_IN_1	P	Power supply input (3.0-3.6V)	—	—	—	—	—	—	—	—	—
31	V_DD_IN_2	P	Power supply input (3.0-3.6V)	—	—	—	—	—	—	—	—	—
32, 33	GND	P	Ground	—	—	—	—	—	—	—	—	—
34	PA8	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA8	—	—	SERCOM1_PAD1	—	—
35	PA7	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA7	—	—	SERCOM1_PAD0	—	TRACECLK
36	PA9	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA9	—	RTC_IN0_ALT	SERCOM1_PAD2	—	—
37	PA10	I/O	PIC32CX-BZ2 Port A Digital I/O	—	—	—	RA10	—	RTC_OUT_ALT	SERCOM1_PAD3	—	—
38	GND	P	Ground	—	—	—	—	—	—	—	—	—
39	IRQ⁽¹¹⁾	I/O	Interrupt request (active-low) from the WINCS02 IC to wake-up the host (PIC32CX-BZ2) from its Sleep state	—	—	—	—	—	—	—	—	—
40	UART2_TX	I/O	UART2 transmit signal for firmware log from WINCS02IC	—	—	—	—	—	—	—	—	—
41	ECC_SCL	I/O	Serial clock input for crypto authentication device on module, NC pin for UE variant	—	—	—	—	—	—	—	—	—
42	ECC_SDA	I/O	Serial data for crypto authentication device on module, NC pin for UE variant	—	—	—	—	—	—	—	—	—
43	NC	I/O	—	—	—	—	—	—	—	—	—	—
44	UART1_TX	I/O	Used for external antenna calibration. Connect this signal to a test point or a pin header.	—	—	—	—	—	—	—	—	—
45–47	NC	I/O	—	—	—	—	—	—	—	—	—	—
48	UART1_RX	I/O	Used for external antenna calibration. Connect this signal to a test point or a pin header.	—	—	—	—	—	—	—	—	—
49	NC	P	—	—	—	—	—	—	—	—	—	—
50	NC	I/O	—	—	—	—	—	—	—	—	—	—
51	Reserved⁽¹⁰⁾	I/O	Reserved pin. Connect to an I/O pin (tri-stated) of a host device or to an external switch for future use	—	—	—	—	—	—	—	—	—
52	W_NMCLR	I	WINCS02IC MCLR Reset	—	—	—	—	—	—	—	—	—
53	DFU_TX/STRAP2	I/O	For WINCS02 device firmware update receive pin. The recommendation is to connect to a pull-down resistor of 100K.	—	—	—	—	—	—	—	—	—
54	DFU_RX/STRAP1	I/O	For WINCS02 device firmware update receive pin. The recommendation is to connect to a pull-down resistor of 100K.	—	—	—	—	—	—	—	—	—
55–58	GND	P	Ground	—	—	—	—	—	—	—	—	—
59, 60	EP GND	P	Thermal ground paddle for connection on host board	—	—	—	—	—	—	—	—	—
Note: All GPIOs (RAn and RBn ) can be used by remappable peripherals via PPS. All GPIOs (RAn and RBn) can be used as I/O Change Notification (IOCAn and IOCBn) except RA11 and RA12. For more details, refer to Port A Register Map for RA11 and RA12 in the PIC32CX-BZ2 and WBZ45 Family Data Sheet (DS70005504). The metal paddle at the bottom of the device must be connected to system ground. These peripherals have signals that are only available via the PPS remappable pins. This pin can be used as Input only pin if not using SOSC and setting up CFGCON2.SOSCSEL = 0. INT0 can be used as a wake-up source from Deep Sleep or Extreme Deep Sleep Low Power modes, as well as an ADC trigger source. The INT0 can be configured using Configuration Control Register 0 (CFGCON0). INT0 functionality on PB4 cannot be remapped using PPS. The software SDK and operational stacks provided by Microchip handles the operation of INT0 as a wake-up source in Deep Sleep Low Power Mode. These I/O pins are 5.5V tolerant: NMCLR, PA0, PA1, PA2, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PB10, PB11, PB12, PB13. All other I/O pins are 3.3V tolerant. The PIC32CX-BZ2 device’s QSPI is configured as SPI to interface with the WINCS02 on the Module PCB. Pin 6 PB1 is used to reset WINCS02 device by driving the pin 52 W_MCLR pin on the PIC32WM-BW1 Curiosity Board (EV60G68A). It is recommended to connect PB1 to W_MCLR on the host-board to avoid changes in software implementation. Do not leave this pin unconnected. Follow the directions in the Pin Description column for future upgrades. Pin 39 IRQ is connected to Pin 9 PB4 on the PIC32WM-BW1 Curiosity Board (EV60G68A). It is recommended to connect IRQ to PB4 on the host-board to avoid changes in software implementation.