2 Device Specific Implementation Details
Some details are specific for the device or device group the accompanying code was written for, thus they may or may not be applicable for other devices. The details described below apply to, but are not necessarily limited to, tinyAVR® 1-series.
Configurable Custom Logic (CCL)
On the tinyAVR® 1-series, the Configurable Custom Logic (CCL) module contains two Look-up Tables (LUTs), taking up to six inputs and generating up to two different outputs.
I/O Pin Controller (PORT) and Port Multiplexer (PORTMUX)
For the tinyAVR® 1-series, the pin used for Hall sensor input in this application is shared with the default output pin of LUT1. The alternate pin for LUT1-OUT is, therefore, used by writing to the CTRLA register of the Port Multiplexer (PORTMUX) module. The specific pins used are listed in the table below.
| Pin | Description | Signal | Module |
|---|---|---|---|
| PA7 | Hall sensor input | P0 | Analog Comparator (AC) |
| PA4 | PWM output A | LUT0-OUT | Configurable Custom Logic (CCL) |
| PC1 | PWM output B | LUT1-OUT | Configurable Custom Logic (CCL) |
16-bit Timer/Counter Type A (TCA)
The accompanying code for this application note uses the default clock settings on the tinyAVR® 1-series, which from the 20 MHz CLK_MAIN and a division factor of 6, give a CLK_PER of 3.33 MHz. The default PWM period is set to 100 timer counts and the default PWM duty cycle is set to 20 timer counts. As the 16-bit Timer/Counter Type A (TCA) is set up with a clock division factor of 1, this corresponds to 30 µs and 6 µs, respectively.
16-bit Timer/Counter Type B (TCB)
The accompanying code for this application note uses the default clock settings on the tinyAVR® 1-series, which from the 20 MHz CLK_MAIN and a division factor of 6, give a CLK_PER of 3.33 MHz. The default dead time is set up to 500 timer counts. As the 16-bit Timer/Counter Type B (TCB) is set up with a clock division factor of 1, this corresponds to 150 µs.