3.10.2 SPI Handling

This section provides an overview of the SPI timings and describes the SPI data transfer in general. The timing is independent from the SPI mode used. Each SPI mode results in the same performance. For more details about the SPI hardware, see SPI – Serial Peripheral Interface from Related Links.

Table 3-13. SPI Timing Example at 500 Kbit/s
Time	Timing at 40% Interrupt Load⁽¹⁾	Description	Depends On	Example
T0	0 or 25 µs	Time from NSS LOW to AVR active (in case AVR sleep mode is enabled)	AVR sleep mode (0 µs, 1 µs or 25 µs)	25 µs
T1	17.6 µs	Time from AVR active to beginning of first telegram byte	Internal IRQ (falling edge)	45 CPU cycles (ISR) + 15 CPU cycles interrupt response time
T2	16 µs	Time to shift in one SPI-byte with SCK	SCK frequency (maximum 500 kHz)	8 bit/500 Kbit/s
T3	—	Pause between two bytes. Can be any length including 0 µs	External microcontroller timing	0 µs
T4	35.1 µs	Time for ATA8210/15 to handle last byte	Depends on SPI command used	Maximum 120 CPU cycles⁽²⁾
T5	16.1 µs	SPI idle time telegram	Internal data processing	40 CPU cycles (ISR) + 15 CPU cycles interrupt response time
Note: Timing calculation done with AVR core of 5.7 MHz Needed for SPI command, Read RX FIFO and Read RSSI FIFO

Table 3-14. CPU Cycles for T4
Read Fill Level RX FIFO	0	Get Version ROM	0
—	—	Get Version Flash	0
Read Fill Level RSSI FIFO	0	Customer Configurable Command	XX
Get Event Bytes	0	System Reset	0
Read RSSI FIFO	120	Trigger EEPROM Secure Write	65
Read RX FIFO	120	Set Voltage Monitor	85
Write SRAM Register	110	OFF Command	0
Read SRAM Register	120	Read Temperature Value	0
Write EEPROM	55	Init SRAM Service	50
Read EEPROM	0	Start RSSI Measurement	55
—	—	Get RSSI Value	0
—	—	Read RX FIFO Byte Interrupt	70
Set System Mode	55	Read RSSI FIFO Byte Interrupt	70
Calibrate and Check	50	—	—
Patch SPI	XX	—	—

SPI Data Transfer Description

After NSS is set to LOW by the external microcontroller, the internal AVR core needs 25 µs to wake up from the configured AVR Sleep mode. If the FRC is kept alive by setting the FRC always-on (FRCAO) EEPROM bit in the clock configuration, the time is reduced to 1 µs. If the system never enters any of the available sleep modes, omit the T0. The falling edge of the NSS line triggers an internal interrupt. This interrupt resets and initializes the software state machine responsible for handling SPI communication. During the interrupt service routing, two event bytes (events.system and events.events) are written to the FIFO SPI output to provide early access to the event status. For this reason, finish the interrupt service routine before the transmission of the first telegram byte starts (T1).

After the communication setup is done (T0 + T1), the system is ready to receive the first byte of data. Data bytes can be written continuously or with a pause (T3) between the bytes. The maximum SCK frequency is 500 kHz, resulting in a maximum data rate of 500 Kbit/s.

The SPI communication is finished by setting NSS back to a logical HIGH level. A certain time, T4, must elapse after transmission of the last byte before allowing the NSS to return to HIGH level. T5 is required to internally process the end of the SPI transfer before receiving the next SPI command.