3.1.2 CLC Description

The Configurable Logic Cell (CLC) is utilized to control the type of clock (non-inverted or inverted) that will be used in constructing the encoder. The decision is taken by implementing a logic XOR gate which gets inputs from the CLK and from the inverted DATA of the EUSART and outputs the DALI-2 frame.

In the case of a non-inverted clock, which starts in logic ‘1’, by writing a logic ‘0’ the XOR gate will output an ‘1’ followed by a ‘0’ during the period of the clock, with the new data having a period two times smaller than the one of the clock.