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PIC16F15256/74/75/76 28/40-Pin Microcontrollers PIC16F15256/74/75/76
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9
Memory Organization
9.2
Data Memory Organization
9.2.5
Common RAM
PIC16F15256/74/75/76
Introduction
PIC16F152
Family Types
Core Features
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F152
Microcontrollers
5
Register and Bit Naming Conventions
6
Register Legend
7
Enhanced Mid-Range CPU
8
Device Configuration
9
Memory Organization
9.1
Program Memory Organization
9.2
Data Memory Organization
9.2.1
Bank Selection
9.2.2
Core Registers
9.2.3
Special Function Register
9.2.4
General Purpose RAM
9.2.5
Common RAM
9.2.6
Device Memory Maps
9.3
STATUS Register
9.4
PCL and PCLATH
9.5
Stack
9.6
Indirect Addressing
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
Resets
11
OSC - Oscillator Module
12
Interrupts
13
Sleep Mode
14
WDT - Watchdog Timer
15
NVM - Nonvolatile Memory Control
16
I/O Ports
17
IOC - Interrupt-on-Change
18
PPS - Peripheral Pin Select Module
19
TMR0 - Timer0 Module
20
TMR1 - Timer1 Module with Gate Control
21
TMR2 - Timer2 Module
22
CCP - Capture/Compare/PWM Module
23
PWM - Pulse-Width Modulation
24
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
25
MSSP - Host Synchronous Serial Port Module
26
FVR - Fixed Voltage Reference
27
ADC - Analog-to-Digital Converter
28
Charge Pump
29
Instruction Set Summary
30
ICSP™ - In-Circuit Serial Programming™
31
Register Summary
32
Electrical Specifications
33
DC and AC Characteristics Graphs and Tables
34
Packaging Information
35
Appendix A: Revision History
Microchip Information
9.2.5 Common RAM
There are 16 bytes of common RAM accessible from all banks.
