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PIC16F15256/74/75/76 28/40-Pin Microcontrollers PIC16F15256/74/75/76
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Product Pages
PIC16F15256
PIC16F15274
PIC16F15275
PIC16F15276
Introduction
PIC16F152
Family Types
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F152
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
Enhanced Mid-Range CPU
7.1
Automatic Interrupt Context Saving
7.2
16
-Level Stack with Overflow and Underflow
7.3
File Select Registers
7.4
Instruction Set
8
Device Configuration
8.1
Configuration Words
8.2
Code Protection
8.3
Write Protection
8.4
User ID
8.5
Device ID and Revision ID
8.6
Register Definitions: Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
9
Memory Organization
9.1
Program Memory Organization
9.2
Data Memory Organization
9.3
STATUS Register
9.4
PCL and PCLATH
9.5
Stack
9.6
Indirect Addressing
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
Resets
10.1
Power-on Reset (POR)
10.2
Brown-out Reset (BOR)
10.3
MCLR
Reset
10.4
Watchdog Timer (WDT) Reset
10.5
RESET
Instruction
10.6
Stack Overflow/Underflow Reset
10.7
Power-Up Timer (PWRT)
10.8
Start-Up Sequence
10.9
Memory Execution Violation
10.10
Determining the Cause of a Reset
10.11
Power Control (PCONx) Register
10.12
Register Definitions: Power Control
10.13
Register Summary - Power Control
11
OSC - Oscillator Module
11.1
Oscillator Module Overview
11.2
Clock Source Types
11.3
Register Definitions: Oscillator Control
11.4
Register Summary - Oscillator Control
12
Interrupts
12.1
INTCON Register
12.2
PIE Registers
12.3
PIR Registers
12.4
Operation
12.5
Interrupt Latency
12.6
Interrupts During Sleep
12.7
INT Pin
12.8
Automatic Context Saving
12.9
Register Definitions: Interrupt Control
12.10
Register Summary - Interrupt Control
13
Sleep Mode
13.1
Sleep Mode Operation
14
WDT - Watchdog Timer
14.1
Selectable Clock Sources
14.2
WDT Operating Modes
14.3
WDT Time-Out Period
14.4
Clearing the WDT
14.5
WDT Operation During Sleep
14.6
Register Definitions: WDT Control
14.7
Register Summary - WDT Control
15
NVM - Nonvolatile Memory Control
15.1
Program Flash Memory (PFM)
15.2
Register Definitions: Nonvolatile Memory Control
15.3
Register Summary - NVM Control
16
I/O Ports
16.1
Overview
16.2
PORTx - Data Register
16.3
LATx - Output Latch
16.4
TRISx - Direction Control
16.5
ANSELx - Analog Control
16.6
WPUx - Weak Pull-Up Control
16.7
INLVLx - Input Threshold Control
16.8
SLRCONx - Slew Rate Control
16.9
ODCONx - Open-Drain Control
16.10
Edge Selectable Interrupt-on-Change
16.11
I
2
C Pad Control
16.12
I/O Priorities
16.13
MCLR
/V
PP
/RE3
Pin
16.14
Register Definitions: Port Control
16.15
Register Summary - IO Ports
17
IOC - Interrupt-on-Change
17.1
Overview
17.2
Enabling the Module
17.3
Individual Pin Configuration
17.4
Interrupt Flags
17.5
Clearing Interrupt Flags
17.6
Operation in Sleep
17.7
Register Definitions: Interrupt-on-Change Control
17.8
Register Summary - Interrupt-on-Change
18
PPS - Peripheral Pin Select Module
18.1
Overview
18.2
PPS Inputs
18.3
PPS Outputs
18.4
Bidirectional Pins
18.5
PPS Lock
18.6
Operation During Sleep
18.7
Effects of a Reset
18.8
Register Definitions: Peripheral Pin Select (PPS)
18.9
Register Summary - Peripheral Pin Select Module
19
TMR0 - Timer0 Module
19.1
Timer0 Operation
19.2
Clock Selection
19.3
Timer0 Output and Interrupt
19.4
Operation During Sleep
19.5
Register Definitions: Timer0 Control
19.6
Register Summary - Timer0
20
TMR1 - Timer1 Module with Gate Control
20.1
Timer1 Operation
20.2
Clock Source Selection
20.3
Timer1 Prescaler
20.4
Timer1 Operation in Asynchronous Counter Mode
20.5
Timer1 16-Bit Read/Write Mode
20.6
Timer1 Gate
20.7
Timer1 Interrupt
20.8
Timer1 Operation During Sleep
20.9
CCP Capture/Compare Time Base
20.10
CCP Special Event Trigger
20.11
Register Definitions: Timer1 Control
20.12
Register Summary - Timer1
21
TMR2 - Timer2 Module
21.1
Timer2 Operation
21.2
Timer2 Output
21.3
External Reset Sources
21.4
Timer2 Interrupt
21.5
PSYNC Bit
21.6
CSYNC Bit
21.7
Operating Modes
21.8
Operation Examples
21.9
Timer2 Operation During Sleep
21.10
Register Definitions: Timer2 Control
21.11
Register Summary - Timer2
22
CCP - Capture/Compare/PWM Module
22.1
CCP Module Configuration
22.2
Capture Mode
22.3
Compare Mode
22.4
PWM Overview
22.5
Register Definitions: CCP Control
22.6
Register Summary - CCP Control
23
PWM - Pulse-Width Modulation
23.1
Fundamental Operation
23.2
PWM Output Polarity
23.3
PWM Period
23.4
PWM Duty Cycle
23.5
PWM Resolution
23.6
Operation in Sleep Mode
23.7
Changes in System Clock Frequency
23.8
Effects of Reset
23.9
Setup for PWM Operation Using PWMx Output Pins
23.10
Setup for PWM Operation to Other Device Peripherals
23.11
Register Definitions: PWM Control
23.12
Register Summary - PWM
24
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
24.1
EUSART Asynchronous Mode
24.2
Clock Accuracy with Asynchronous Operation
24.3
EUSART Baud Rate Generator (BRG)
24.4
EUSART Synchronous Mode
24.5
EUSART Operation During Sleep
24.6
Register Definitions: EUSART Control
24.7
Register Summary - EUSART
25
MSSP - Host Synchronous Serial Port Module
25.1
SPI Mode Overview
25.2
I
2
C Mode Overview
25.3
Baud Rate Generator
25.4
Register Definitions: MSSP Control
25.5
Register Summary - MSSP Control
26
FVR - Fixed Voltage Reference
26.1
Independent Gain Amplifiers
26.2
FVR Stabilization Period
26.3
Register Definitions: FVR
26.4
Register Summary - FVR
27
ADC - Analog-to-Digital Converter
27.1
ADC Configuration
27.2
ADC Operation
27.3
ADC Acquisition Requirements
27.4
Register Definitions: ADC Control
27.5
Register Summary - ADC
28
Charge Pump
28.1
Manually Enabled
28.2
Automatically Enabled
28.3
Disabled
28.4
Charge Pump Threshold
28.5
Charge Pump Ready
28.6
Register Definitions: Charge Pump
29
Instruction Set Summary
29.1
Read-Modify-Write Operations
29.2
Standard Instruction Set
30
ICSP™ - In-Circuit Serial Programming™
30.1
High-Voltage Programming Entry Mode
30.2
Low-Voltage Programming Entry Mode
30.3
Common Programming Interfaces
31
Register Summary
32
Electrical Specifications
32.1
Absolute Maximum Ratings
(†)
32.2
Standard Operating Conditions
32.3
DC Characteristics
32.4
AC Characteristics
33
DC and AC Characteristics Graphs and Tables
33.1
Analog-to-Digital Converter (10-bit) Graphs
33.2
Band Gap Ready Graphs
33.3
Brown-Out Reset Graphs
33.4
Fixed Voltage Reference Graphs
33.5
HFINTOSC Error Graphs
33.6
HFINTOSC Wake From Sleep Graphs
33.7
I/O Rise/Fall Times Graphs
33.8
I
DD
Graphs
33.9
Input Buffer Graphs
33.10
I
PD
Graphs
33.11
LFINTOSC Graphs
33.12
OSCTUNE Graphs
33.13
Power-On Reset Graphs
33.14
V
OH
- V
OL
Graphs
33.15
Watchdog Timer Graphs
33.16
Weak Pull-Up Graphs
34
Packaging Information
34.1
Package Details
35
Appendix A: Revision History
Microchip Information
The Microchip Website
Product Change Notification Service
Customer Support
Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
