4.5 Clear Buffer/FIFOS

As previously mentioned, the transmission FIFO (TXFIFO) is written by software and the receive FIFO (RXFIFO) is written by the SPI module as data is shifted in from the slave. This SPI module allows the user to reset the occupancy for both FIFOs and clear the SPI buffers. To clear the SPI buffers, the CLRBF bit of the SPIxSTATUS register must be set high. Please note that the transmit and receive FIFOs are also reset when the SPI module is disabled. Clearing the buffers is an optional step, but can be useful in ensuring that the SPI does not have any existing data sitting in the buffer at the start of a data exchange.