2.2 Clock Sources

The SPIxCLK register allows the user to select different clock sources. The SPIxBAUD register is used for dividing the clock source selected to generate the SCK output signal. The frequency of the SCK output signal is defined by the equation below.

$F_{BAUD}=\frac{F_{CSEL}}{\left(\right(2\times BAUD)+1)}$

where F_BAUD is that baud rate frequency output on the SCK pin, F_CSEL is the frequency of the input clock selected by the SPIxCLK register, and BAUD is the value of the SPIxBAUD register.

In the SPI protocol, there are four different configurations that control the timing of data transmissions. The configuration of the Clock Edge Select bit (CKE) and the Clock Polarity Select bit (CKP) are used to configure the SPI master to match the mode of the other devices on the SPI bus. The most common mode for SPI slave communication is when data is sampled at the leading rising edge of the clock (CKP = 0 / CKE = 0). It is important to check the SPI slave device specifications to ensure that the proper polarity and clock edge settings have been made for the SPI master. Refer to the device data sheet for more information about how the CKP and CKE bits affect SPI clocking.

The complete list of registers associated with this peripheral, along with their descriptions, can be found in the device data sheet.