5.1 SPI Receiver Data Interrupt

The SPI receiver data interrupt is set when the receive FIFO contains data, and cleared when the FIFO is empty. For DMA-based operation the user does not need to enable the receive interrupt required for another operation. The status of the SPI receiver data interrupt flag can be monitored by reading the SPIxRXIF bit located in the device peripheral interrupt registers.

The DMA module can be configured to shift data from the receive FIFO to another memory region on the PIC microcontroller. This allows the SPI to keep receiving data without software involvement to keep the receive FIFO from filling up. The example below shows how to configure the DMA to take data from the RXFIFO and store it in Flash memory as it is being received.

// DMA Configuration (Source SPI1RXB)
DMA1CON0 = 0xC0; // DMA Enable; SIRQEN;
DMA1CON1 = 0x0B; // DMODE; SMR; SMODE; SSTP;
DMA1SSA = &SPI1RXB; // DMA Source Start Address - SPI1RXB;
DMA1SSZ = 0x01; // DMA Source Size ();
DMA1DSA = 0x1000; // DMA Destination Start Address ();
DMA1DSZ = 0x32; // DMA Destination Size ();
DMA1SIRQ = 0x14; // DMA Start Interrupt Request Source (SPI1RXB:20);