6.67.2 Status Register (SREG) and Boolean Formula


I	T	H	S	V	N	Z	C
–	–	–	–	–	–	–	–

Example:

      clr   r29       ; Clear Y high byte
      ldi   r28,0x60  ; Set Y low byte to 0x60
      ld    r0,Y+     ; Load r0 with data space loc. 0x60(Y post inc)
      ld    r1,Y      ; Load r1 with data space loc. 0x61
      ldi   r28,0x63  ; Set Y low byte to 0x63
      ld    r2,Y      ; Load r2 with data space loc. 0x63
      ld    r3,-Y     ; Load r3 with data space loc. 0x62(Y pre dec)
      ldd   r4,Y+2    ; Load r4 with data space loc. 0x64

Words: 1 (2 bytes)

Table 6-67. Cycles
Name	Cycles
Name	i	ii	iii	iv
AVRe	2⁽¹⁾	2⁽¹⁾	2⁽¹⁾	2⁽¹⁾
AVRxm	2⁽¹⁾⁽³⁾	2⁽¹⁾⁽³⁾	3⁽¹⁾⁽³⁾	3⁽¹⁾⁽³⁾
AVRxt	2⁽²⁾	2⁽²⁾	2⁽²⁾	2⁽²⁾
AVRrc	1 / 2	2 / 3	2 / 3	N/A

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.
Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM. A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more information.
If the LD instruction is accessing I/O Registers, one cycle can be deducted.