6.70.2 Status Register (SREG) and Boolean Formula


I	T	H	S	V	N	Z	C
–	–	–	–	–	–	–	–

Example:

      lds   r2,0xFF00  ; Load r2 with the contents of data space location 0xFF00
      add   r2,r1      ; add r1 to r2
      sts   0xFF00,r2  ; Write back

Words: 2 (4 bytes)

Table 6-70. Cycles
Name	Cycles
AVRe	2⁽¹⁾
AVRxm	3⁽¹⁾⁽³⁾
AVRxt	3⁽²⁾
AVRrc	N/A

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.
Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM. A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more information.
If the LD instruction is accessing I/O Registers, one cycle can be deducted.