6.114.2 Status Register (SREG) and Boolean Formula


I	T	H	S	V	N	Z	C
–	–	–	–	–	–	–	–

Example:

      clr   r27        ; Clear X high byte
      ldi   r26,0x60   ; Set X low byte to 0x60
      st    X+,r0      ; Store r0 in data space loc. 0x60(X post inc)
      st    X,r1       ; Store r1 in data space loc. 0x61
      ldi   r26,0x63   ; Set X low byte to 0x63
      st    X,r2       ; Store r2 in data space loc. 0x63
      st    -X,r3      ; Store r3 in data space loc. 0x62(X pre dec)

Words: 1 (2 bytes)

Table 6-114. Cycles
Name	Cycles
Name	(i)	(ii)	(iii)
AVRe	2⁽¹⁾	2⁽¹⁾	2⁽¹⁾
AVRxm	1⁽¹⁾	1⁽¹⁾	2⁽¹⁾
AVRxt	1⁽²⁾	1⁽²⁾	1⁽²⁾
AVRrc	1	1	2

Note:

Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.
Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM. A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more information.