6.20.2 Status Register (SREG) and Boolean Formula


I	T	H	S	V	N	Z	C
–	–	–	–	–	–	–	–

Example:

      eor   r19,r19   ; Clear r19
loop: inc   r19       ; Increase r19
      ...
      cpi   r19,0x10  ; Compare r19 with 0x10
      brlo  loop      ; Branch if r19 < 0x10 (unsigned)
      nop             ; Exit from loop (do nothing)

Words: 1 (2 bytes)

Table 6-20. Cycles
Name	Cycles
Name	i	ii
AVRe	1	2
AVRxm	1	2
AVRxt	1	2
AVRrc	1	2

i) If the condition is false.

ii) If the condition is true.

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