6.55.2 Status Register (SREG) and Boolean Formula
| I | T | H | S | V | N | Z | C |
| – | – | – | – | – | – | ⇔ | ⇔ |
- C
-
R16
Set if bit 15 of the result before the left shift is set; cleared otherwise.
- Z
-
R15 ∧ R14 ∧ R13 ∧ R12 ∧ R11 ∧ R10 ∧ R9 ∧ R8∧R7 ∧ R6 ∧ R5 ∧ R4 ∧ R3 ∧ R2 ∧ R1 ∧ R0
Set if the result is
0x0000; cleared otherwise.
R (Result) equals R1,R0 after the operation.
Example:
;******************************************************************************
;* DESCRIPTION
;* Signed fractional multiply of two 16-bit numbers with 32-bit result.
;* USAGE
;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;******************************************************************************
fmuls16x16_32:
clr r2
fmuls r23, r21 ; ((signed)ah * (signed)bh) << 1
movw r18, r0
fmul r22, r20 ; (al * bl) << 1
adc r18, r2
movw r16, r0
fmulsu r23, r20 ; ((signed)ah * bl) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
fmulsu r21, r22 ; ((signed)bh * al) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
ret
- Words
- 1 (2 bytes)
| Name | Cycles |
|---|---|
| AVRe | 2 |
| AVRxm | 2 |
| AVRxt | 2 |
| AVRrc | N/A |
