6.2.2 Status Register (SREG) and Boolean Formula

H

Rd3 ∧ Rr3 ∨ Rr3 ∧ R3 ∨ R3 ∧ Rd3

Set if there was a carry from bit 3; cleared otherwise.

S

N ⊕ V, for signed tests.

V

Rd7 ∧ Rr7 ∧ R7 ∨ Rd7 ∧ Rr7 ∧ R7

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7 ∧ R6 ∧ R5 ∧ R4 ∧ R3 ∧ R2 ∧ R1 ∧ R0

Set if the result is 0x00; cleared otherwise.

C

Rd7 ∧ Rr7 ∨ Rr7 ∧ R7 ∨ R7 ∧ Rd7

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      add   r1,r2       ; Add r2 to r1 (r1=r1+r2)
      add   r28,r28     ; Add r28 to itself (r28=r28+r28)

Words

1 (2 bytes)