6.82.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
0
S
N ⊕ V, for signed tests.
V

0

Cleared.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7R6R5R4R3R2R1R0

Set if the result is 0x00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      or    r15,r16   ; Do bitwise or between registers
      bst   r15,6     ; Store bit 6 of r15 in T bit
      brts  ok        ; Branch if T bit set
      ...
ok: 
      nop             ; Branch destination (do nothing)
Words
1 (2 bytes)
Table 6-82. Cycles
NameCycles
AVRe1
AVRxm1
AVRxt1
AVRrc1