6.89.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
1–––––––
I

1

The I flag is set.

Example: 

      ... 
extint:
      push  r0  ; Save r0 on the Stack
      ...
      pop   r0  ; Restore r0
      reti      ; Return and enable interrupts
Words
1 (2 bytes)
Table 6-89. Cycles
NameCycles
9/16-bit PC22-bit PC
AVRe4(2)5(2)
AVRxm4(2)5(2)
AVRxt45
AVRrc6N/A
Note:
  1. RETI behaves differently in AVRe, AVRxm, and AVRxt devices. In the AVRe series of devices, the Global Interrupt Enable bit is cleared by hardware once an interrupt occurs, and this bit is set when RETI is executed. In the AVRxm and AVRxt devices, RETI will not modify the Global Interrupt Enable bit in SREG since it is not cleared by hardware while entering ISR. This bit should be modified using SEI and CLI instructions when needed.
  2. Cycle times for data memory access assume internal RAM access and are not valid for accessing external RAM.