6.54.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
–––⇔0⇔⇔–
S
N ⊕ V, for signed tests.
V

0

Cleared.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7 ∧ R6 ∧ R5 ∧ R4 ∧ R3 ∧ R2 ∧ R1 ∧ R0

Set if the result is 0x00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      eor   r4,r4    ; Clear r4
      eor   r0,r22   ; Bitwise exclusive or between r0 and r22
Words
1 (2 bytes)
Table 6-54. Cycles
NameCycles
AVRe1
AVRxm1
AVRxt1
AVRrc1