6.5.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
0
S
N ⊕ V, for signed tests.
V

0

Cleared.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7R6R5R4R3R2R1R0

Set if the result is 0x00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      andi  r17,0x0F      ; Clear upper nibble of r17
      andi  r18,0x10      ; Isolate bit 4 in r18
      andi  r19,0xAA      ; Clear odd bits of r19
Words
1 (2 bytes)
Table 6-5. Cycles
NameCycles
AVRe1
AVRxm1
AVRxt1
AVRrc1