6.49.2 Status Register and Boolean Formula

ITHSVNZC
S
N ⊕ V, for signed tests.
V

R7 ∧ R6 ∧ R5 ∧ R4 ∧ R3 ∧ R2 ∧ R1 ∧ R0

Set if two’s complement overflow resulted from the operation; cleared otherwise. Two’s complement overflow occurs only if Rd was 0x80 before the operation.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7R6R5R4R3R2R1R0

Set if the result is 0x00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      ldi   r17,0x10  ; Load constant in r17
loop:
      add   r1,r2     ; Add r2 to r1
      dec   r17       ; Decrement r17
      brne  loop      ; Branch if r17<>0
      nop             ; Continue (do nothing)
Words
1 (2 bytes)
Table 6-49. Cycles
NameCycles
AVRe1
AVRxm1
AVRxt1
AVRrc1