6.56.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
C

R16

Set if bit 15 of the result before the left shift is set; cleared otherwise.

Z

R15R14R13R12R11R10R9R8R7R6R5R4R3R2R1R0

Set if the result is 0x0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

      fmuls r23,r22     ; Multiply signed r23 and r22 in (1.7) format, 
                        ; result in (1.15) format
      movw  r22,r0      ; Copy result back in r23:r22
Words
1 (2 bytes)
Table 6-56. Cycles
NameCycles
AVRe2
AVRxm2
AVRxt2
AVRrcN/A