6.50.1 Description

The module is an instruction set extension to the AVR CPU, performing DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in the CPU Register File, registers R0-R7, where the LSB of data is placed in the LSB of R0 and the MSB of data is placed in the MSB of R7. The full 64-bit key (including parity bits) is placed in registers R8-R15, organized in the Register File with the LSB of the key in the LSB of R8 and the MSB of the key in the MSB of R15. Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext. Intermediate results are stored in the Register File (R0-R15) after each DES instruction. The instruction's operand (K) determines which round is executed, and the Half Carry (H) flag determines whether encryption or decryption is performed.

The DES algorithm is described in “Specifications for the Data Encryption Standard” (Federal Information Processing Standards Publication 46). Intermediate results in this implementation differ from the standard because the initial permutation and the inverse initial permutation are performed in each iteration. This does not affect the result in the final ciphertext or plaintext but reduces the execution time.


	Operation:
(i)	If H == 0 then Encrypt round (R7-R0, R15-R8, K) If H == 1 then Decrypt round (R7-R0, R15-R8, K)
	Syntax:	Operands:	Program Counter:
(i)	DES K	`0x00`≤K≤`0x0F`	PC ← PC + 1

16-bit Opcode:


1001	0100	KKKK	1011

Example:

      des   0x00
      des   0x01
      …
      des   0x0E
      des   0x0F

Words: 1 (2 bytes)

Table 6-50. Cycles
Name	Cycles
AVRe	N/A
AVRxm	1 / 2
AVRxt	N/A
AVRrc	N/A

Note: If the DES instruction is succeeding a non-DES instruction, it requires two cycles otherwise one.