6.4.2 Status Register (SREG) and Boolean Formula

ITHSVNZC
0
S
N ⊕ V, for signed tests.
V

0

Cleared.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7R6R5R4R3R2R1R0

Set if the result is 0x00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

      and   r2,r3     ; Bitwise and r2 and r3, result in r2
      ldi   r16,1     ; Set bitmask 0000 0001 in r16
      and   r2,r16    ; Isolate bit 0 in r2
Words
1 (2 bytes)
Table 6-4. Cycles
NameCycles
AVRe1
AVRxm1
AVRxt1
AVRrc1