20.3.11 PORTWCLK

Signal Routing Port Clock Selection

Note: This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.

Name:	PORTWCLK
Offset:	0x010A


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] Signal Routing Port Clock Input Selection

Table 20-2. Signal Routing Port Clock Input Selections
Value	Description
`11111`	Reserved
`11110`	PORTWCLKPPS
`11101`	TU16B_OUT
`11100`	TU16A_OUT
`11011`	NCO1_OUT
`11010`	TMR4_OUT
`11001`	TMR2_OUT
`11000`	CLC8_OUT
`10111`	CLC7_OUT
`10110`	CLC6_OUT
`10101`	CLC5_OUT
`10100`	CLC4_OUT
`10011`	CLC3_OUT
`10010`	CLC2_OUT
`10001`	CLC1_OUT
`10000`	Reserved
`01111`	Reserved
`01110`	TMR3_OUT
`01101`	TMR1_OUT
`01100`	PWM2S1P2_OUT
`01011`	PWM2S1P1_OUT
`01010`	PWM1S1P2_OUT
`01001`	PWM1S1P1_OUT
`01000`	CCP1_OUT
`00111`	CLKREF_OUT
`00110`	EXTOSC
`00101`	SOSC
`00100`	MFINTOSC (32 kHz)
`00011`	MFINTOSC (500 kHz)
`00010`	LFINTOSC
`00001`	HFINTOSC
`00000`	F_OSC

Reset States:

POR/BOR = 00000

All Other Resets = 00000

This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.

DS40002671A

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.