16.13.13 DMAnSIRQ

DMA Start Interrupt Request Source Selection Register
Name: DMAnSIRQ
Offset: 0x0FE

Bit 76543210 
 SIRQ[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – SIRQ[7:0] DMA Start Interrupt Request Source Selection

Table 16-6. DMAxSIRQ and DMAxAIRQ Interrupt Sources
ValueDescriptionValue

(cont.)

Description

(cont.)

0x0-0x35SPI1TX
0x1HLVD (High/Low-Voltage Detect)0x36SPI1
0x2OSF (Oscillator Fail)0x37-
0x3CSW (Clock Switching)0x38TU16A (Universal Timer 16A)
0x4NVM0x39TU16B (Universal Timer 16B)
0x5SCAN0x3ATMR1
0x6CRC (Cyclic Redundancy Check)0x3BTMR1G
0x7IOC (Interrupt-On-Change)0x3CTMR3
0x8INT00x3DTMR3G
0x9ADT (ADC Threshold Interrupt)0x3ETMR2
0xAAD (ADC Conversion Complete)0x3FTMR4
0xBACT (Active Clock Tuning)0x40CWG1 (Complementary Waveform Generator)
0xCCLB0 (Configurable Logic Block)0x41NCO1 (Numerically Controlled Oscillator)
0xDCLB10x42CCP1
0xECLB20x43TMR0
0xFCLB30x44PWM1R
0x10CLC1 (Configurable Logic Cell)0x45PWM1G
0x11CLC20x46PWM2R
0x12CLC30x47PWM2G
0x13CLC40x48CM1 (Comparator)
0x14CLC50x49CM2
0x15CLC60x4A-0x4F-
0x16CLC70x50INT1
0x17CLC80x51INT2
0x18DMA1SCNT (Direct Memory Access)0x52-0x57-
0x19DMA1DCNT0x58IOCSR (Interrupt-On-Change Signal Routing Ports)
0x1ADMA1OR0x59ZCD1 (Zero-Cross Detection)
0x1BDMA1A0x5A-
0x1CDMA2SCNT0x5B-
0x1DDMA2DCNT0x5CVDDIO2LVDFIF
0x1EDMA2OR0x5DVDDIO2LVDRIF
0x1FDMA2A0x5EVDDIO2PORFIF
0x20DMA3SCNT0x5FVDDIO2PORRIF
0x21DMA3DCNT0x60PWM1S1P1 (PWM1 Parameter 1 of Slice 1)
0x22DMA3OR0x61PWM1S1P2 (PWM1 Parameter 1 of Slice 2)
0x23DMA3A0x62PWM2S1P1
0x24DMA4SCNT0x63PWM2S1P2
0x25DMA4DCNT0x64-
0x26DMA4OR0x65-
0x27DMA4A0x66TU16APR
0x28U1RX0x67TU16ACAPT
0x29U1TX0x68TU16AZERO
0x2AU1E0x69TU16BPR
0x2BU10x6ATU16BCAPT
0x2CU2RX0x6BTU16BZERO
0x2DU2TX0x6CPORTW IOC Flag (RW0)
0x2EU2E0x6DPORTW IOC Flag (RW1)
0x2FU20x6EPORTW IOC Flag (RW2)
0x30I2C1RX0x6FPORTW IOC Flag (RW3)
0x31I2C1TX0x70PORTW IOC Flag (RW4)
0x32I2C10x71PORTW IOC Flag (RW5)
0x33I2C1E0x72PORTW IOC Flag (RW6)
0x34SPI1RX0x73PORTW IOC Flag (RW7)